ST72561J6 STMicroelectronics, ST72561J6 Datasheet - Page 42
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ST72561J6
Manufacturer Part Number
ST72561J6
Description
8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
Manufacturer
STMicroelectronics
Datasheet
1.ST72561R9.pdf
(265 pages)
Specifications of ST72561J6
Hdflash Endurance
100 cycles, data retention 40 years at 85°C
5 Power Saving Modes
Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow
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ST72561
POWER SAVING MODES (Cont’d)
Figure 27. ACTIVE HALT Timing Overview
Figure 28. ACTIVE HALT Mode Flow-chart
42/265
(Active Halt enabled)
(AWUCSR.AWUEN=0)
INSTRUCTION
HALT INSTRUCTION
RUN
N
(MCCSR.OIE=1)
HALT
INTERRUPT
ACTIVE
HALT
Y
DELAY (AFTER RESET)
256 OR 4096 CYCLE
INTERRUPT
3)
RESET
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
FETCH RESET VECTOR
OR
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
CPU
I[1:0] BITS
N
CYCLE DELAY
RESET
Y
VECTOR
2)
FETCH
XX
XX
OFF
OFF
OFF
RUN
ON
ON
ON
ON
ON
ON
10
4)
4)
Notes:
1. This delay occurs only if the MCU exits ACTIVE
2. Peripheral clocked with an external clock
3. Only the RTC interrupt and some specific inter-
4. Before servicing an interrupt, the CC register is
HALT mode by means of a RESET.
source can still be active.
rupts can exit the MCU from ACTIVE HALT
mode (such as external interrupt). Refer to
Table 9, “Interrupt Mapping,” on page 34
more details.
pushed on the stack. The I[1:0] bits in the CC
register are set to the current software priority
level of the interrupt routine and restored when
the CC register is popped.
for
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