ST72561J6 STMicroelectronics, ST72561J6 Datasheet - Page 190

• Manufacturer Part Number: ST72561J6
• Description: 8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
• Manufacturer: STMicroelectronics

Specifications of ST72561J6

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

ST72561
beCAN CONTROLLER (Cont’d)
Side-effect of Workround 1
Because the while loop lasts 10 CPU cycles, at
high baud rate, it is possible to miss a dominant
state on the bus if it lasts just one CAN bit time and
the bus speed is high enough (see
Table 29. While Loop Timing
If this happens, we will continue waiting in the
while loop instead of releasing the FIFO immedi-
ately. The workaround is still valid because we will
not release the FIFO during the critical period. But
the application may lose additional time waiting in
the while loop as we are no longer able to guaran-
tee a maximum of 6 CAN bit times spent in the
workaround.
In this particular case the time the application can
spend in the workaround may increase up to a full
CAN frame, depending of the frame contents. This
Figure 113. Reception at Maximum CAN Baud Rate
190/265
Sampling of Rx pin
8 MHz
4 MHz
CAN Bus signal
f
f
CPU
CPU
While loop
Software
10/f
1.25 µs
timing:
2.5 µs
CPU
R
R
Minimum baud rate for
R
possible missed
dominant bit
800 Kbaud
400 Kbaud
Table
R
f
CPU
D
/10
R
1).
R
R
R
D
case is very rare but happens when a specific se-
quence is present on in the CAN frame.
The example in
imum CAN baud rate: In this case t
and the sampling time is 10/f
If the application is using the maximum baud rate
and the possible delay caused by the workaround
is not acceptable, there is another workaround
which reduces the Rx pin sampling time.
Workaround 2 (see
FMP = 2 and the CAN cell is receiving, if not the
FIFO can be released immediately. If yes, the pro-
gram goes through a sequence of test instructions
on the RX pin that last longer than the time be-
tween the acknowledge dominant bit and the criti-
cal time slot. If the Rx pin is in recessive state for
more than 8 CAN bit times, it means we are now
after the acknowledge and the critical slot. If a
dominant bit is read on the bus, we can release the
FIFO immediately. This workaround has to be writ-
ten in assembly language to avoid the compiler
optimizing the test sequence.
The implementation shown here is for the CAN
bus maximum speed (1 Mbaud @ 8 MHz CPU
clock).
R
R
R
R
D
Figure 20
R
R
Figure
R
shows reception at max-
R
CPU
21) first tests that
D
.
R
R
CAN
R
is 8/f
R
D
CPU