ST72561J6 STMicroelectronics, ST72561J6 Datasheet - Page 244
ST72561J6
Manufacturer Part Number
ST72561J6
Description
8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
Manufacturer
STMicroelectronics
Datasheet
1.ST72561R9.pdf
(265 pages)
Specifications of ST72561J6
Hdflash Endurance
100 cycles, data retention 40 years at 85°C
5 Power Saving Modes
Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow
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ST72561
COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d)
Figure 139. SPI Slave Timing Diagram with CPHA = 1
Figure 140. SPI Master Timing Diagram
Notes:
1. Measurement points are done at CMOS levels: 0.3 x V
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
244/265
MISO
MOSI
MISO
MOSI
SS
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
SS
OUTPUT
INPUT
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
CPOL = 0
CPHA = 1
CPOL = 1
INPUT
INPUT
OUTPUT
INPUT
See
note 2
See note 2
t
a(SO)
t
su(SS)
Hz
t
t
t
v(MO)
t
w(SCKH)
w(SCKL)
su(MI)
t
su(SI)
MSB OUT
MSB IN
MSB OUT
t
h(MO)
t
MSB IN
h(MI)
t
h(SI)
1)
t
c(SCK)
t
c(SCK)
t
t
t
v(SO)
w(SCKH)
w(SCKL)
DD
BIT6 OUT
and 0.7 x V
BIT6 OUT
BIT6 IN
1)
DD
BIT1 IN
.
t
h(SO)
t
t
t
t
r(SCK)
f(SCK)
r(SCK)
f(SCK)
LSB OUT
LSB IN
LSB OUT
LSB IN
t
h(SS)
t
See note 2
dis(SO)
See
note 2
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