ST72361J6 STMicroelectronics, ST72361J6 Datasheet - Page 116

• Manufacturer Part Number: ST72361J6
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72361J6

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

ST72361
SERIAL PERIPHERAL INTERFACE (cont’d)
10.6.6 Low Power Modes
10.6.6.1 Using the SPI to wake up the device
from Halt mode
In slave configuration, the SPI is able to wake up
the device from HALT mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from HALT mode, if the
SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring
116/225
Mode
WAIT
HALT
No effect on SPI.
SPI interrupt events cause the device to exit
from WAIT mode.
SPI registers are frozen.
In HALT mode, the SPI is inactive. SPI oper-
ation resumes when the device is woken up
by an interrupt with “exit from HALT mode”
capability. The data received is subsequently
read from the SPIDR register when the soft-
ware is running (interrupt vector fetching). If
several data are received before the wake-
up event, then an overrun error is generated.
This error can be detected after the fetch of
the interrupt routine that woke up the Device.
Description
the SPI from HALT mode state to normal state. If
the SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake up the device from
HALT mode only if the Slave Select signal (exter-
nal SS pin or the SSI bit in the SPICSR register) is
low when the device enters HALT mode. So, if
Slave selection is configured as external (see
tion
level on the SS pin when the slave enters HALT
mode.
10.6.7 Interrupts
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
SPI End of
Transfer Event
Master Mode
Fault Event
Overrun Error
Interrupt Event
10.6.3.2), make sure the master drives a low
MODF
Event
SPIF
OVR
Flag
Control
Enable
SPIE
Bit
from
Wait
Exit
Yes
from
Exit
Halt
Yes
No
Sec-