ST72361J6 STMicroelectronics, ST72361J6 Datasheet - Page 35

• Manufacturer Part Number: ST72361J6
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72361J6

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

INTERRUPTS (Cont’d)
7.6.2 Register Description
EXTERNAL INTERRUPT CONTROL
REGISTER 0 (EICR0)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 7:6 = IS3[1:0] ei3 sensitivity
The interrupt sensitivity, defined using the IS3[1:0]
bits, is applied to the ei3 external interrupts:
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 5:4 = IS2[1:0] ei2 sensitivity
The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the ei2 external interrupts:
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 3:2 = IS1[1:0] ei1 sensitivity
The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the ei1 external interrupts:
IS31 IS30
IS21 IS20
IS11 IS10
IS31
0
0
1
1
0
0
1
1
0
0
1
1
7
IS30
0
1
0
1
0
1
0
1
0
1
0
1
IS21
External Interrupt Sensitivity
External Interrupt Sensitivity
External Interrupt Sensitivity
IS20
Falling edge & low level
Falling edge & low level
Falling edge & low level
Rising and falling edge
Rising and falling edge
Rising and falling edge
Falling edge only
Falling edge only
Falling edge only
Rising edge only
Rising edge only
Rising edge only
IS11
IS10
IS01
IS00
0
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
Bits 1:0 = IS0[1:0] ei0 sensitivity
The interrupt sensitivity, defined using the IS0[1:0]
bits, is applied to the ei0 external interrupts:
These 2 bits can be written only when I1 and I0 of
the CC register are both set to 1 (level 3).
EXTERNAL INTERUPT CONTROL REGISTER 1
(EICR1)
Read / Write
Reset Value: 0000 0000 (00h)
BIts 7:2 = Reserved
Bit 1 = TLIS Top Level Interrupt sensitivity
This bit configures the TLI edge sensitivity. It can
be set and cleared by software only when TLIE bit
is cleared.
0: Falling edge
1: Rising edge
Bit 0 = TLIE Top Level Interrupt enable
This bit allows to enable or disable the TLI capabil-
ity on the dedicated pin. It is set and cleared by
software.
0: TLI disabled
1: TLI enabled
Notes:
– A parasitic interrupt can be generated when
– In some packages, the TLI pin is not available. In
IS01 IS00
clearing the TLIE bit.
this case, the TLIE bit must be kept low to avoid
parasitic TLI interrupts.
0
0
1
1
7
0
0
1
0
1
0
0
External Interrupt Sensitivity
Falling edge & low level
Rising and falling edge
0
Falling edge only
Rising edge only
0
0
TLIS
ST72361
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TLIE
0