ST72361J6 STMicroelectronics, ST72361J6 Datasheet - Page 97

• Manufacturer Part Number: ST72361J6
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72361J6

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

8-BIT TIMER (Cont’d)
Notes:
1. Once the OCIE bit is set both output compare
2. If the OCiE bit is not set, the OCMPi pin is a
3. When the timer clock is f
4. The output compare functions can be used both
5. The value in the 8-bit OC
Figure 65. Output Compare Block Diagram
8-bit
features may trigger interrupt requests. If only
one is needed in the application, the interrupt
routine software needs to discard the unwanted
compare interrupt. This can be done by check-
ing the OCF1 and OCF2 flags and resetting
them both.
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
OCMPi are set while the counter value equals
the OCiR register value (see
99). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f
8000, OCFi and OCMPi are set while the coun-
ter value equals the OCiR register value plus 1
(see
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
OLVi bit should be changed after each suc-
8 BIT
OC1R Register
OUTPUT COMPARE
8-bit
Figure 67 on page
CIRCUIT
OC2R Register
FREE RUNNING
COUNTER
8-bit
99).
CPU
i
R register and the
CPU
Figure 66 on page
/4, f
/2, OCFi and
OC1E
CPU
/8 or f
OCIE
OC2E
OCF1
CPU
/
FOLV2 FOLV1
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit = 1). The OCFi bit is then
not set by hardware, and thus no interrupt request
is generated.
The FOLVLi bits have no effect in both one pulse
mode and PWM mode.
(Control Register 2) CR2
(Control Register 1) CR1
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
OCF2
CC1
(Status Register) SR
OLVL2
CC0
0
0
OLVL1
0
Latch
Latch
1
2
ST72361
OCMP1
OCMP2
Pin
Pin
97/225