DS80C410 Maxim, DS80C410 Datasheet
DS80C410
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DS80C410 Summary of contents
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... Peripherals include a 10/100 Ethernet MAC, three serial ports, an optional CAN 2.0B controller, 1-Wire® Master, and 64 I/O pins. The DS80C410 and DS80C411 also include 64kBytes internal SRAM for user application storage and network stack. To enable access to the network, a full application- accessible TCP IPv4/6 network stack and OS are provided in the ROM ...
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... Soldering Temperature………………………………………………………………See IPC/JEDEC J-STD-020 Standard Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied ...
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... Note 11: Following the one-shot timeout, ports in I/O mode source transition current when being pulled down externally. It reaches a maximum at approximately 2V. Note 12: During external addressing mode, weak latches are used to maintain the previously driven state on the pin until such time that the Port 0 pin is driven by an external memory source ...
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AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER External Crystal Frequency Clock Mutliplier 2X Mode Clock Multiplier 4X Mode External Clock Oscillator Frequency Clock Mutliplier 2X Mode Clock Multiplier ...
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... Note 1: Figure 21 shows a detailed description and illustration of the system clock selection. Note 2: When an external clock oscillator is used in conjunction with the default system clock selection (CD1:CD0 = 10b), the minimum/maximum system clock high (t MOVX CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS) (Note 3.0V to 3.6V 1.8V ±10%, T CC3 ...
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PARAMETER SYMBOL Data Float After RD (P3 RHDZ PSEN) High ALE Low to Valid Data In t LLDV Port 0 Address to Valid Data t AVDV0 In Port Address, Port 4 CE, or Port 5 ...
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MULTIPLEXED, 2-CYCLE DATA MEMORY PCE0-3 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 MULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − ...
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MULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 MULTIPLEXED, 3-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0 − 3 PORT 6 – ...
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MULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 MULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 − 3 PORT 6 – CE4 − ...
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... A16 -A21 MULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 A16 -A21 A16 -A21 ADDRESS DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN A16 -A21 A16 -A21 A16 -A21 12 of 102 A16 -A21 A16 -A21 ...
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MULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 A16 -A21 A16 -A21 ADDRESS A16 -A21 13 of 102 A16 -A21 ...
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ELECTRICAL CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER External Crystal Frequency Clock Mutliplier 2X Mode Clock Multiplier 4X Mode External Oscillator Frequency Clock Mutliplier 2X Mode Clock Multiplier 4X Mode ...
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MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS 3.0V to 3.6V 1.8V +±10%, T CC3 CC1 PARAMETER Input Instruction Float After PSEN PSEN High to Data Address, Port 4 CE, Port 5 PCE Valid RD Pulse Width (P3.7 or ...
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Note 1: AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production tested, but are guaranteed by design. Note 2: All parameters apply to both commercial and industrial temperature operation, unless ...
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NONMULTIPLEXED, 2-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 NONMULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – ...
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NONMULTIPLEXED, 2-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 PORT 7 NONMULTIPLEXED, 3-CYCLE DATA MEMORY PCE0-3 READ OR WRITE PORT 4 – CE0 − 3 PORT ...
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NONMULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 PORT 7 NONMULTIPLEXED, 3-CYCLE DATA MEMORY CE0-7 WRITE PORT 4 – CE0 − 3 PORT 6 – ...
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... PORT 7 NONMULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 READ PORT 4 – CE0 − 3 PORT 6 – CE4 − 7 PORT 4/6 ADDRESS A16 -A21 A16 -A21 PORT 7 DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN A16 -A21 A16 -A21 A16 -A21 22 of 102 A16 -A21 A16 -A21 ...
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... Note 4: This parameter quantifies the wait time for the case when no presence pulse detected. Note 5: The maximum timing figures shown apply only when an exact 1-Wire clock frequency can be achieved from the microcontroller input clock. A16 -A21 A16 -A21 = -40°C to +85°C.) ...
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OW PIN TIMING 24 of 102 ...
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PIN TIMING CHARACTERISTICS OWSTP (V = 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER Active Time for Presence Detect Active Time for Presence Detect Recovery Active Time for Write 1 Recovery (Notes 2, 3) Active Time for ...
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ETHERNET MII INTERFACE TIMING CHARACTERISTICS (V = 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER TXClk Duty Cycle TXD, TX_EN Data Setup to TXClk TXD, TX_EN Data Hold from TXClk RXClk Pulse Width RXClk to RXD, RX_DV, ...
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SERIAL PORT MODE 0 TIMING CHARACTERISTICS (V = 3.0V to 3.6V 1.8V ±10%, T CC3 CC1 PARAMETER Serial Port Clock Cycle Time Output Data Setup to Clock Rising Output Data Hold from Clock Rising Input Data Hold After ...
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SERIAL PORT 0 (SYNCHRONOUS MODE) HIGH-SPEED OPERATION, TXD CLK = SYSCLK/4 (SM2 = 1) TRADITIONAL 8051 OPERATION, TXD CLOCK = XTAL/12 (SM2 = 102 ...
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POWER-CYCLE TIMING CHARACTERISTICS PARAMETER Crystal Startup Time (Note 1) Power-On Reset Delay (Note 2) Note 1: Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by Fox Electronics. Note 2: Reset ...
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... BLOCK DIAGRAM 1-WIRE CONTROLLER PORT LATCH PORT 5 P5.0–P5.7 DS80C410 DS80C411 P1.0–P1.7 PORT 1 SERIAL PORT 1 PORT LATCH TIMER 102 P0.0–P0.7 PORT 0 ...
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PIN DESCRIPTION PIN NAME 70 V +1.8V Core Supply Voltage CC1 12, 36, 62, V +3.3V I/O Supply Voltage CC3 87 13, 39, 63, V Digital Circuit Ground SS 88 Address Latch Enable, Output. When the MUX pin is low, ...
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PIN NAME P2.4 A12 Program/Data Memory Address 12 58 A14 P2.5 A13 Program/Data Memory Address 13 P2.6 A14 Program/Data Memory Address 14 57 A15 P2.7 A15 Program/Data Memory Address 15 Port 3, I/O. Port 3 functions as an 8-bit, bidirectional ...
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... Ethernet PHY controller as a timing referenced for transferring information on the MDIO pin. MDC is a periodic 18 MDC signal that has no maximum high or low times. The minimum high and low times are 160ns each. The minimum period for MDC is 400ns independent of the period of TXClk and RXClk. FUNCTION ...
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PIN NAME MII Management Input/Output. The MII management I/O is the data pin for serial communication with the external Ethernet PHY controller read cycle, data is driven by the PHY to the MAC synchronously with 19 MDIO respect ...
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... TERMINOLOGY The term DS80C410 is used in the remainder of the document to refer to the DS80C410 and DS80C411 unless otherwise specified. DETAILED DESCRIPTION The DS80C410 network microcontroller offers the highest integration available in an 8051 device. Peripherals include a 10/100 Ethernet MAC, three serial ports, an optional CAN 2.0B controller, 1-Wire Master, and 64 I/O pins. ...
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... In its default configuration (machine cycle = 4 oscillator cycles), the DS80C410 executes the “MOVX A, @DPTR” instruction in as little as two machine cycles or 8 oscillator cycles, but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times ...
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... SFRs control most special features of the microcontroller. They allow the device to have many new features but use the standard 8051 instruction set. When writing software to use a new feature, an equate statement defines the SFR to the assembler or compiler. This is the only change needed to access the new function. The DS80C410 duplicates the SFRs contained in the standard 80C32. ...
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Table 1. SFR Addresses and Bit Locations REGISTER BIT 7 BIT 6 P4 P4.7/A19 P4.6/A18 SP DPL DPH DPL1 DPH1 DPS ID1 ID0 PCON SMOD_0 SMOD0 TCON TF1 TR1 TMOD GATE C/T TL0 TL1 TH0 TH1 CKCON WD1 WD0 P1 ...
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REGISTER BIT 7 BIT 6 C0M9C MSRDY ETI C0M10C MSRDY ETI IP — PS1 SADEN0 SADEN1 C0M11C MSRDY ETI C0M12C MSRDY ETI C0M13C MSRDY ETI C0M14C MSRDY ETI C0M15C MSRDY ETI SCON1 SM0/FE_1 SM1_1 SBUF1 PMR CD1 CD0 STATUS PIP ...
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REGISTER BIT 7 BIT 6 DPL3 DPH3 DPS1 ID3 ID2 STATUS1 — — EIP EPMIP C0IP P7 P7.7/A7 P7.6/A6 TL3 TH3 T3CM TF3 TR3 SCON2 SM0/FE_2 SM1_2 SBUF2 Note: Shaded bits are timed-access protected. BIT 5 BIT 4 BIT 3 ...
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Table 2. SFR Reset Values REGISTER BIT 7 BIT DPL 0 0 DPH 0 0 DPL1 0 0 DPH1 0 0 DPS 0 0 PCON 0 0 TCON 0 0 TMOD 0 0 ...
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REGISTER BIT 7 BIT 6 STATUS 0 0 MCON T2CON 0 0 T2MOD 1 1 RCAP2L 0 0 RCAP2H 0 0 TL2 0 0 TH2 0 0 COR 0 1 PSW 0 0 MCNT0 0 ...
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... Up to 16MB of external code memory can be addressed through a multiplexed or demultiplexed 22-bit address bus/8-bit data bus through eight available chip enables 4MB of external data memory can be accessed over the same address/data buses through peripheral-enable signals. The DS80C410 also permits a 16MB merged program/data memory map. ...
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... The 16-bit address mode accesses memory in a similar manner as a traditional 8051 op-code compatible with the 8051 microprocessor and identical to the byte and cycle count of the Maxim high-speed microcontroller family. A device operating in this mode can access up to 64kB of program and data memory. The DS80C410 defaults to this mode following any reset. ...
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... P6CNT.2-0 = 111b. External Data Memory Addressing Using a similar implementation as was used to expand program memory access, the DS80C410 allows up to 4MB of data memory access through four peripheral chip enables (PCE). The Port 5 control register (P5CNT; A2h) and Port 6 control register (P6CNT; B2h) designate the number of peripheral chip enables and the maximum amount of addressable data memory per peripheral chip enable ...
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... When combined program/data memory access is enabled, there is the potential to inadvertently modify code that a user meant to leave fixed. For this reason, the DS80C410 provides the ability to write protect the first 0–16kB of memory accessible through each of the chip enables CE3, CE2, CE1, and CE0. The write-protection feature for each chip enable is invoked by setting the appropriate WPE3– ...
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... The registers making up the second, third, and fourth data pointers are located at SFR address locations not used in the original 8051. To access the extended 24-bit address range supported by the DS80C410, a third, high-order byte (DPXn) has been added to each pointer so that each data pointer is now composed of the SFR combination DPXn+DPHn+DPLn. ...
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... SEL are not implemented so that the INC DPS instruction can still be used to quickly toggle between DPTR0 and DPTR1 or between DPTR2 and DPTR3. Unlike the standard 8051, the DS80C410 has the ability to decrement as well as increment the data pointers without additional instructions. Each data pointer (DPTR0, DPTR1, DPTR2, DPTR3) has an associated control bit (ID0, ID1, ID2, ID3) that determines whether the INC DPTR operation results in an increment or decrement of the pointer ...
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... MOVX @DPTR, A Stretch Memory Cycles The DS80C410 allows user-application software to select the number of machine cycles it takes to execute a MOVX instruction, allowing access to both fast and slow off-chip data memory and/or peripherals without glue logic. High-speed systems often include memory-mapped peripherals such as LCDs or UARTs with slow access times may not be necessary or desirable to access external devices at full speed ...
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... The 8kB (2kx32) block is used by the Ethernet MAC as frame-buffer memory for incoming or outgoing packet data and can, at the same time, be accessed by the DS80C410 as MOVX data memory. While the MAC is in use, special care should be taken by user software to prevent undesirable MOVX writes from corrupting frame-buffer memory ...
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... Extended Stack Pointer The DS80C410 supports both the traditional 8-bit and an extended 10-bit stack pointer that improves the performance of large programs written in high-level languages such enable the 10-bit stack pointer, set the stack-address mode bit, SA (ACON.2). The bit is cleared following a reset, forcing the device to use an 8-bit stack located in the scratchpad RAM area ...
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... ENDEC mode operation. The system clock (external clock source after internal multiplication or division) must be a minimum of 25MHz for use of the Ethernet 100Mbps mode. For half-duplex mode operation, the DS80C410 shares the Ethernet physical media with other stations on the network. The DS80C410 follows the IEEE 802.3 carrier-sense multiple-access with collision detection (CSMA/CD) method for accessing the physical media ...
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... CSMA/CD) needs to be used. For full-duplex operation, the flow control mechanism is the PAUSE control frame. When needing time to free additional receive data buffers, the DS80C410 can initiate a PAUSE control frame, requesting that the other station suspend transmission attempts for a specified number of time slots ...
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... Buffer Control Unit The buffer control unit (BCU) serves as the central controller of all DS80C410 Ethernet activity. The BCU regulates CPU read/write activity to the Ethernet controller blocks through a series of SFRs: BCU control (BCUC; E7h), BCU data (BCUD; E6h), CSR address (CSRA; E4h), and CSR data (CSRD; E3h). These SFRs allows the CPU to issue commands to the BCU, exchange packet size/location information with the BCU, configure the on-chip Ethernet MAC, and even communicate with external PHYs through the MII serial-management bus ...
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The BCU incorporates first-in-first-out receive packet register (receive FIFO) so that the CPU can access information for the next receive packet in queue. Upon reception of each valid packet into receive buffer memory, the BCU ...
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Each CSR register is documented as follows: CSR Register: MAC Control Register Address: 00h Bit Names BLE 23 DRO OM[1: — 7 BLOMT[1:0] Reset State ...
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IF, Inverse Filtering 0 = inverse filtering disabled (default inverse filtering by the address check block enabled PB, Pass Bad Frames 0 = packet filter bit in the receive status word is set (= 1) only when error-free ...
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CSR Register: MAC Address High Register Address: 04h Bit Names: 31 — — 23 — — Reset State PADR [47:32]m MAC Physical Address [47:32]. These two ...
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CSR Register: Multicast Address High Register Address: 0Ch Bit Names: 31 HT[63] HT[62] 23 HT[55] HT[54] 15 HT[47] HT[46] 7 HT[39] HT[38] Reset State [63:32], Hash Table ...
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CSR Register: MII Address Register Address: 14h Bit Names: 31 — — 23 — — 15 PHYA [4:0] 7 PHYR [1:0] Reset State PHYA[4:0], PHY Address [4:0]. This ...
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... Upon successful transmission of a pause-control frame, the BUSY bit returns to logic pause-control frame currently being transmitted (default initiate a pause-control frame Figure 4. Pause-Control Frame SFD PREAMBLE (7) (1) (6) DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN PAUSE [15:8] PAUSE [7:0] — — — — — — 0 ...
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CSR Register: VLAN1 Tag Register Address: 20h Bit Names: 31 — — 23 — — Reset State VLAN1 [15:0], VLAN1 Tag Identifier [15:0]. These 16 bits ...
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CSR Register: Wake-Up Frame Filter Register Address: 28h Bit Names Reset State WUFD [31:0], Wake-Up Frame Filter Data [31:0]. These 32 bits are used ...
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... Media Independent Interface (MII) The DS80C410 contains an IEEE 802.3 MII-compliant PHY interface. This interface contains two basic blocks. The MII I/O block provides independent transmit and receive data-path I/O and PHY network-status signal inputs. The MII management block implements a 2-wire serial communication bus to facilitate PHY register access. The block ...
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... MII I/O Block The MII I/O block supports all of the transmit and receive data transactions between the DS80C410 MAC and the external PHY device as well as monitoring network status signals provided by the PHY. The transmit interface is composed of TXCLK, TX_EN, and TXD[3:0]. The TXCLK input is the transmit clock provided by the PHY ...
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... Unless specifically disabled through the disable broadcast frame (DBF) bit in the CSR MAC control register (00h), broadcast frames are always received by the DS80C410 MAC. The address filter criteria are established using five bits found in the CSR MAC control register (00h). Three basic filter possibilities exist: perfect, inverse, and hash ...
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... CRC-32 GENERATOR VLAN Support The DS80C410 offers VLAN support through recognition of frames that are tagged as such. Each VLAN tag provides tag control information (TCI) containing a tag protocol ID (TPID) and VLAN ID. The incoming TPID occupy the 13th and 14th byte positions, those that would normally contain either the length or type field for the frame. The TPID is compared against the VLAN1 (20h) and VLAN2 (24h) CSR registers ...
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... Transmit/Receive Packet Buffer Memory (8kB) The DS80C410 Ethernet controller uses 8kB of internal SRAM as transmit/receive packet buffer memory. This SRAM is read/write accessible as data memory by the CPU using the MOVX instruction. The BCU also has access to this SRAM, and automatically writes/reads packet buffer memory whenever it needs to store or retrieve Ethernet packet information ...
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Transmit/Receive Status Words For each attempt made by the MAC to receive or transmit packet data, the BCU writes a 32-bit transmit or receive status word back to the first word of the starting page for the packet. This word ...
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NOCRS, No Carrier. This bit is only valid in half-duplex mode transmit frame was not aborted due to lack of carrier 1 = transmit frame aborted due to lack of carrier (CRS = 0 when transmit frame initiated) ...
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... LONG, Frame Too Long. This bit only serves as a status indicator and does not cause frame truncation receive frame did not exceed the maximum frame length check 1 = receive frame exceeded the maximum frame length (1518 Bytes, unless VLAN tagged) RUNT, Runt Frame 0 = receive frame is not a runt frame (< ...
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... BCU reports the status of either a transmit or receive packet. Power Management Block The DS80C410 Ethernet controller contains a power management block that allows put into a sleep mode by the CPU, thus conserving power when not actively handling Ethernet traffic. ...
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... DS80C410 ROM code. These two controls are the EA pin and the bypass ROM (BROM) SFR bit. No matter the state of the BROM bit, if the EA pin is held at a logic low level, the DS80C410 ROM code is not entered and is not accessible to the user code. If the EA pin logic high level, the BROM bit is then examined to determine whether the internal DS80C410 ROM should be executed or bypassed ...
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Figure 13. ROM Code Boot Sequence Figure 13 illustrates the ROM decisions 74 of 102 ...
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... DS80C410 ROM Initialization Code The DS80C410 firmware automatically executes Initialization Code (ROM_Init) to generate the memory map as shown in Figure 14 and configure the hardware as follows: Enables 24-bit contiguous address mode Logically relocates ROM to addresses FF0000h–FF7FFFh Enables CE0–3, 2MB/chip enable Enables PCE0–3 Enables CE4– ...
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... The calculated reload value and clock frequency can be used in the equation to solve for the baud rate configurable by the DS80C410 advised that the baud rate mismatch be no greater than ±2.5% to maintain reliable communication. The functionality was designed to work for clock rates from 3.680MHz to 75 ...
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... ADDRESS FROM DS2502 TFTP/FLASH WRITE Next, the DS80C410 ROM searches the 1-Wire bus for an external device (separate from the device containing the MAC address) that contains an IP address and TFTP server IP address. In order to correctly acquire the IP and TFTP server addresses from an external 1-Wire device, the data read from the device must conform to a specific format ...
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... IP addresses). When option 150 is present in the acknowledge packet, it will take precedence over the “next server IP” field. Now armed with an IP address and TFTP server IP address, the DS80C410 tries to find code to be loaded into external program memory. The DS80C410 ROM first requests to read the file from the TFTP server coinciding with a “ ...
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... In order for user application code to call a specific function, the location of that function must be known. The absolute address location of each DS80C410 ROM function must be read from an export table (also found in the ROM). To allow flexibility for future ROM firmware structural changes and improvements, the export table itself is not connected to a specific address range, but instead a 3-Byte pointer to the start of the export table is fixed at addresses FF0002h (XSB), FF0003h (MSB), and FF0004h (LSB) ...
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... ROM export table. Brief descriptions of the functionality FF0000h Function [2] Address Function [3] Address FFxxxxh . . . Function [n] Address FFFFFFh 80 of 102 DS80C410 ROM (LOGICALLY LOCATED FF0000h– FFFFFFh WHEN MROM = 1) Export Table Address ROM Exported Function [ ROM Export Table ...
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Table 16. ROM Export Table INDEX FUNCTION 0 Num_Fn,0,0 1 crc16 2 mem_clear 3 mem_copy 4 mem_compare 5 add_dptr0 6 add_dptr1 7 sub_dptr0 8 sub_dptr1 9 getpseudorandom 10 rom_kernelmalloc 11 rom_kernelfree 12 rom_malloc 13 rom_malloc_dirty 14 rom_free 15 rom_deref 16 ...
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... BOOT_MEMBEGIN 92 BOOT_MEMEND 93 OWM_First 94 OWM_Next 95 OWM_Reset 96 OWM_Byte 97 OWM_Search 98 OWM_ROMID 99 Autobaud 100 tftp_close Note: Index 101 and higher only available on DS80C410 or ROM 1.2.0 and newer 101 ROM_NetBoot 102 task_switcher 103 Tick_CalculateReload 104 OWM_ProbeClock 105 OWM_CalculateDivisor 106 Info_SendString 107 Info_SendTwoHex 108 Info_ConvHex 109 Info_SendCRLF 110 ...
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INDEX FUNCTION 122 Math_LongDiv1024 123 task_suspend_nc 123 task_sleep_nc 124 UDP_TestReceive 125 ETH_ReadMII 126 ETH_WriteMII 127 ETH_ReadCSR 128 ETH_WriteCSR 129 IP_CheckHeader 130 IP_PacketReceived DESCRIPTION/GROUP Task scheduler functions Socket function Ethernet MAC functions IP stack functions 83 of 102 ...
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... TCP/IP Stack and Berkeley Sockets The ROM firmware implements TCP/IP Ethernet networking over an industry-standard/Berkeley socket interface. The stack supports TCP and UDP transport protocols, allowing a maximum of 24 client/server sockets for either IPv4 or IPv6. Table 17 lists the socket functions implemented and accessible in the ROM firmware. The full details of each socket function are contained in the High-Speed Microcontroller User’ ...
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... SFR map. The remaining registers associated with the message centers (data identification, identification/arbitration masks, format and data) are located in MOVX data space. For the DS80C410, the message centers are fixed from FFDB00h – FFDBFFh. ...
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Modification of the CAN registers located in MOVX memory is protected through the SWINT bit. Consult the description of this bit in the High-Speed Microcontroller User’s Guide: Network Microcontroller Supplement for more information. The CAN module contains a block of ...
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... Note that message center 15 can only be used in a receive mode. To avoid a priority inversion, the DS80C410 CAN controller is configured to reload the transmit buffer with the message of the highest priority (lowest message center number) whenever an arbitration is lost or an error condition occurs. ...
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Table 19. Arbitration/Masking Feature Summary ARBITRATION TEST NAME REGISTERS Message Center Standard 11-bit Arbitration Registers 0–1 Arbitration (Located in each message (CAN 2.0A) center, MOVX memory) Message Center Extended 29-bit Arbitration Registers 0–3 Arbitration (Located in each message (CAN 2.0B) ...
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... SWINT bit when TSEG1 and TSEG2 are both cleared to 0. 1-Wire Bus Master The DS80C410 incorporates a 1-Wire bus master to support communication to external 1-Wire devices. The bus master provides complete control of the 1-Wire bus and coordinates transmit (Tx)/receive (Rx) activities with minimal supervision by the CPU ...
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Clock Control All 1-Wire timing patterns are generated using a base clock of 1.0MHz. To create this base clock frequency for the 1-Wire bus master, the microcontroller system clock must be internally divided down. The clock divisor internal register implements ...
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... These commands are generated through the setting of a corresponding bit in the command register (xxxxx000h). These operational modes are defined in The Book of iButton Standards available on our website at www.maxim-ic.com/iButtonBook. 1WR (Bit 0): 1-Wire Reset. Setting this bit to logic 1 causes a reset of the 1-Wire bus, which must precede any command given on the bus ...
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EN_FOW (Bit 2): Enable Force OW. Setting the EN_FOW bit to a logic 1 allows the bus master to force the OW line low using FOW (bit 2 of the command register). Clearing the EN_FOW bit to a logic 0 ...
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... Peripheral Overview (Primary Integrated System Logic) The DS80C410 provides several of the most commonly needed peripheral functions in microcomputer-based systems. The DS80C410 offers three serial ports, four timers, a programmable watchdog timer, power-fail reset detection, and a power-fail interrupt flag. Each of these peripherals is described below, and more details are available in the High-Speed Microcontroller User’ ...
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Timers The microcontroller provides four general-purpose timer/counters. Timers 0, 1, and 3 have three common modes of operation. Each of the three can be used as a 13-bit timer/counter, 16-bit timer/counter, or 8-bit timer/counter with auto-reload. Timer 0 can also ...
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... IrDA Clock The DS80C410 has the ability to generate an output clock (CLKO secondary function on port pin P3.5. Setting both the IrDA clock-output enable bit (IRDACK:COR.7) and external clock-output enable bit (XCLKOE:COR. logic 1 produces an output clock of 16 times the programmed baud rate for serial port 0. ...
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... Interrupt flag register are accessed in the same way. One’s Complement Adder The DS80C410 implements a one’s complement adder to support the Internet checksum algorithm. The adder contains a 16-bit accumulator and is accessed through the one’s complement adder data (OCAD) SFR. ...
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... Clock Control and Power Management The DS80C410 includes a number of unique features that allow flexibility in selecting system clock sources and operating frequencies. To support the use of inexpensive crystals while allowing full speed operation, a clock multiplier is included in the microcontroller’s clock circuit. Also, in addition to the standard 80C32 idle and power- down (stop) modes, the DS80C410 provides a PMM ...
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Changing the System Clock/Machine Cycle Clock Frequency The microcontroller incorporates a special locking sequence to ensure “glitch-free” switching of the internal clock signals. All changes to the CD1, CD0 bits must pass through the 10 (divide-by-4) state. For example, to ...
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Status The STATUS (C5h) register and STATUS1 (F7h) register provide information about interrupt and serial port activity to assist in determining possible to enter PMM. The microcontroller supports three levels of interrupt priority: power-fail, high, and low. ...
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... External Reset Pins The DS80C410 has both reset input (RST) and reset output (RSTOL) pins. The RSTOL pin supplies an active-low reset output when the microcontroller is reset through a high on the RST pin, a timeout of the watchdog timer, a crystal oscillator fail internally detected power-fail. The timing of the RSTOL pin is dependent on the source of the reset ...
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... XTAL/4. Software Breakpoint Mode The DS80C410 provides a special software-breakpoint mode for code-debug purposes. Breakpoint mode can be enabled by setting the BPME bit (ACON. logic 1. Once enabled, the A5h op code can be used to create a break in code execution. When the break op code (A5h) is executed, all clocks to the timer and watchdog timer blocks are stopped and any serial port operation (when derived from a timer) is halted ...
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... © 2009 Maxim Integrated Products DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN DESCRIPTION 102 of 102 Maxim is a registered trademark of Maxim Integrated Products, Inc ...