DS80C410 Maxim, DS80C410 Datasheet - Page 49

• Manufacturer Part Number: DS80C410
• Description: The DS80C410/DS80C411 network microcontrollers offer the highest integration available in an 8051 device
• Manufacturer: Maxim

DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
Auto-Increment/Decrement (if AID = 1)
MOVC A, @A+DPTR
MOVX A, @DPTR
MOVX @DPTR, A
When used in conjunction, the auto-toggle and auto-increment/decrement features can produce very fast and
efficient routines for copying or moving data. For example, suppose you want to copy three bytes of data from a
source location (pointed to by DPTR2) to a destination location (pointed to by DPTR3). Assuming that DPTR2 is
the active pointer (SEL1 = 1, SEL = 0), with TSL = 1 and AID = 1, the instruction sequence below copies the three
bytes:
MOVX A, @DPTR
MOVX @DPTR, A
MOVX A, @DPTR
MOVX @DPTR, A
MOVX A, @DPTR
MOVX @DPTR, A
Stretch Memory Cycles
The DS80C410 allows user-application software to select the number of machine cycles it takes to execute a
MOVX instruction, allowing access to both fast and slow off-chip data memory and/or peripherals without glue
logic. High-speed systems often include memory-mapped peripherals such as LCDs or UARTs with slow access
times, so it may not be necessary or desirable to access external devices at full speed. The microprocessor can
perform a MOVX instruction in as little as two machine cycles or as many as 12 machine cycles. Accesses to
internal MOVX SRAM always use two cycles. Note that stretch cycle settings affect external MOVX memory
operations only and there is no way to slow the accesses to program memory other than to use a slower crystal (or
external clock).
External MOVX timing is governed by the selection of 0-to-7 stretch cycles, controlled by the MD2–MD0 SFR bits in
the clock control register (CKCON.2–0). A stretch of 0 results in a 2-machine cycle MOVX instruction. A stretch of 7
results in a MOVX of 12 machine cycles. Software can dynamically change the stretch value depending on the
particular memory or peripheral being accessed. The default of one stretch cycle allows the use of commonly
available SRAMs without dramatically lengthening the memory access times.
Stretch cycle settings affect external MOVX timing in three gradations. Changing the stretch value from 0 to 1 adds
an additional clock cycle each to the data setup and hold times. Stretch values of 2 and 3 each stretch the WR or
RD signal by an additional machine cycle. When a stretch value of 4 or above is selected, the interface timing
changes dramatically to allow for very slow peripherals. First, the ALE signal is lengthened by one machine cycle.
This increases the address setup time into the peripheral by this amount. Next, the address is held on the bus for
one additional machine cycle, increasing the address hold time by this amount. The WR and RD signals are then
lengthened by a machine cycle. Finally, during a MOVX write the data is held on the bus for one additional machine
cycle, thereby increasing the data hold time by this amount. For every stretch value greater than 4, the setup and
hold times remain constant, and only the width of the read or write signal is increased. These three gradations are
reflected in the AC Electrical Characteristics section, where the eight MOVX timing specifications are represented
by only three timing diagrams.
The reset default of one stretch cycle results in a three-cycle MOVX for any external access. Therefore, the default
off-chip RAM access is not at full speed. This is a convenience to existing designs that use slower RAM. When
maximum speed is desired, software should select a stretch value of 0. When using very slow RAM or peripherals,
the application software can select a larger stretch value.
The specific timing of MOVX instructions as a function of stretch settings is provided in the Electrical Specifications
section of this data sheet. As an example,
Table 9
shows the read and write strobe widths corresponding to each
stretch value.
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