DS80C410 Maxim, DS80C410 Datasheet - Page 73

• Manufacturer Part Number: DS80C410
• Description: The DS80C410/DS80C411 network microcontrollers offer the highest integration available in an 8051 device
• Manufacturer: Maxim

Figure 12. Wake-Up Frame-Filter Structure
31
RESERVED
Embedded ROM Firmware
The DS80C410 incorporates an embedded ROM specifically designed for hosting the MxTNI™ runtime
environment and the MxTNI C libraries. The ROM firmware implements three major components: a full TCP/IPv4/6
stack with industry-standard Berkeley socket interface, a preemptive task scheduler, and NetBoot functionality. The
NetBoot component uses the TCP/IP stack, socket layer, and task scheduler to provide automatic network boot
capability. NetBoot allows an application to be downloaded from the network and executed by the microcontroller.
To use the ROM firmware, the system is required to have the following hardware components:
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Selecting DS80C410 ROM Code Execution
The DS80C410, following each reset, begins execution of program code at address location 000000h. Since the
DS80C410 contains internal ROM and supports external program code, the user must select which of these two
program memory spaces should be accessed for initial program fetching. There are two mechanisms that control
selection of the internal DS80C410 ROM code. These two controls are the EA pin and the bypass ROM (BROM)
SFR bit. No matter the state of the BROM bit, if the EA pin is held at a logic low level, the DS80C410 ROM code is
not entered and is not accessible to the user code. If the EA pin is at a logic high level, the BROM bit is then
examined to determine whether the internal DS80C410 ROM should be executed or bypassed. If BROM = 0, the
ROM code is executed. Otherwise (BROM = 1), the ROM code is bypassed and execution is transferred to external
user code at address 000000h. The BROM bit defaults to 0 on a power-on reset, but is unaffected by other reset
sources. This code selection process can be seen in
DS80C410 ROM Code Execution Flow
Once the internal DS80C410 ROM code has been selected (EA = 1, BROM = 0), it must first execute some basic
configuration code to provide functionality to subsequent ROM operations. Next, the ROM code reads the state of
port pin P1.7. The ROM associates the logic state of P1.7 with the user desire to invoke the serial loader function. If
the serial loader pin (P1.7) is a logic 1, the ROM monitors for activity on serial port 0 and tries to respond to the
external host with its own serial banner. Once serial communication has been established at a supported baud
rate, signified by correct reception of the DS80C410 loader banner and prompt, the user can issue commands. The
serial loader commands are described later in the data sheet. If the serial loader pin is pulled to a logic 0, the ROM
reads the state of port pin P5.3. Much like the association made between P1.7 and invocation of the serial loader,
the ROM links the logic state of P5.3 with the user desire to begin the NetBoot process. If the NetBoot pin (P5.3) is
asserted (logic 0), the ROM initiates the NetBoot process. If the NetBoot pin is not asserted (logic 1), the ROM
MxTNI is a trademark of Maxim Integrated Products, Inc.
Note 1:
Note 2:
Note 3:
FILTER 3 OFFSET
64kB SRAM memory, internal on the DS80C410 and DS80C411, mapped (Note 1) at address locations
000000h–00FFFFh
Memory (SRAM or flash) to store user-application code
DS2502P-E48 1-Wire chip, to hold physical MAC address (Note 2)
External crystal or oscillator (Note 3)
Merged program/data memory configuration is required.
Java applications and NetBoot require a DS2502P-E48. Applications written in C can program the MAC address directly and do not
require the use of the DS2502P-E48.
NetBoot functionality requires external clock frequency to be at least 7MHz. Clock doubler is not turned on until after NetBoot. Thus,
100Mbps NetBoot is not possible unless the external clock source is at least 25MHz. When not in NetBoot, the system clock
(external clock source after internal multiplication or division) must be a minimum of 25MHz for use of the Ethernet 100Mbps mode.
COMMAND
FILTER 3
FILTER 1 CRC-16
FILTER 3 CRC-16
RESERVED
FILTER 2 OFFSET
COMMAND
FILTER 2
FILTER 0 BYTE MASK
FILTER 1 BYTE MASK
FILTER 2 BYTE MASK
FILTER 3 BYTE MASK
73 of 102
Figure
RESERVED
13.
FILTER 1 OFFSET
COMMAND
FILTER 1
FILTER 0 CRC-16
FILTER 2 CRC-16
RESERVED
FILTER 0 OFFSET
COMMAND
FILTER 0
0