73S1217F Maxim, 73S1217F Datasheet - Page 102

• Manufacturer Part Number: 73S1217F
• Description: The Teridian 73S1217F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

Protocol Mode Register (SPrtcol): 0xFE0D
This register determines the protocol to be use when communicating with the selected smart card. This
register should be updated as required when switching between smart card interfaces.
102
SPrtcol.7
SPrtcol.6
SPrtcol.5
SPrtcol.4
SPrtcol.3
SPrtcol.2
SPrtcol.1
SPrtcol.0
Bit
MSB
SCISYN
MOD9/8B
SCESYN
RCVATR
SCISYN
Symbol
TMODE
CRCMS
CRCEN
0
MOD9/8B SCESYN
Smart Card Internal Synchronous mode – Configures internal smart card
interface for synchronous mode. This mode routes the internal interface
buffers for RST, IO, C4, C8 to
CLK is generated by the ETU counter.
Synchronous 8/9 bit mode select – For sync mode, in protocols with 9-bit
words, set this bit. The first eight bits read go into the RX FIFO and the
ninth bit read will be stored in the IO (or SIO) data bit of the
register.
Smart Card External Synchronous mode – Configures External Smart Card
interface for synchronous mode. This mode routes the external smart card
interface buffers for SIO to
SCLK is generated by the ETU counter.
Reserved bit, must always be set to 0.
Protocol mode select – 0: T=0, 1: T=1. Determines which smart card
protocol is to be used during message processing.
CRC Enable – 1 = Enabled, 0 = Disabled. Enables the
checking/generation of CRC/LRC while in T=1 mode. Has no effect in T=0
mode. If enabled and a message is being transmitted to the smart card,
the CRC/LRC will be inserted into the message stream after the last TX
byte is transmitted to the smart card. If enabled, CRC/LRC will be checked
on incoming messages and the value made available to the firmware via
the CRC LS/MS registers.
CRC Mode Select – 1 = CRC, 0 = LRC. Determines type of checking
algorithm to be used.
Receive ATR – 1 = Enable ATR timeout, 0 = Disable ATR timeout. Set by
firmware after the smart card has been turned on and the hardware is
expecting ATR.
Table 92: The SPrtcol Register
0
0x03
TMODE
SCECtl
SCCtl
Function
register bits for direct firmware control.
register bits for direct firmware control.
CRCEN
CRCMS
SRXCtl
RCVATR
LSB
Rev. 1.2