73S1217F Maxim, 73S1217F Datasheet - Page 139

• Manufacturer Part Number: 73S1217F
• Description: The Teridian 73S1217F is a self-contained SoC smart card reader IC that is an ideal solution for any USB-connected ISO 7816 design
• Manufacturer: Maxim

Rev. 1.2
PGADDR
(see detailed description above).”
In
In
In
FUSECtl bit description to TRIMPCtl.
In
In
In
Added the RTCTrim0 and ACOMP registers. Deleted the OMP, VRCtl,
LEDCal and LOCKCtl registers.
In
In
In
In the
paragraphs about MPU clock rates of 12MHz or greater, changing the
MPU clock rate or the number of wait states.
Changed the register address for
In
the activation sequence begins (either by VCCOK=1 or VCCTMR timeout)
and will go high ½ the ETU period thereafter.”
In
into three primary types. These are commonly referred to as 2-wire, 3-
wire and I2C synchronous cards. Each card type requires different control
and timing and therefore requires different algorithms to access. Teridian
has created an application note to provide detailed algorithms for each
card type. Refer to the application note titled 73S12xxF Synchronous
Card Design Application Note.”
In
Replaced
In
SCISYN (SPrtcol, bit 7) with I2CMODE.
In
In
Added
Added
Formatted the document per new standard. Added section numbering.
Table
Table
Table
Table
Table
Table
Table
Figure
Table
Section
Section
Table 85
Table
Figure 27
Section
Miscellaneous Control Register 1 (MISCtl1)
Section 6, Related
Section 7, Contact
3, changed “FLSHCRL” to “FLSHCTL”.
5, removed the PREBOOT bit description.
5, moved the TRIMPCtl bit description to FUSECtl and moved the
6, changed “PGADR” to “PGADDR”.
7, added PGADDR.
8, changed the reset value for RTCCtl from “0x81” to “0x00”.
11, removed Mcount entries 7, 8, 9 and 10.
22, corrected the descriptions for TCON.2 and TCON.0.
114, replaced SYCKST (STXCtl, bit 7) with I2CMODE and
4, removed CPUCLK.
Figure
register, added “Note: the page address is shifted left by one bit
1.7.17.5, deleted “The ETU clock is held in reset condition until
1.7.17.5, added “Synchronous card operation is broken down
3.4, changed the Fxtal Min value from 4 to 6.
and
and
Table
Figure
23,
Figure
114, changed the SYCKST bit to I2CMODE.
28, replaced the schematics with new schematics.
Documentation.
Information.
24, and
ATRMsB
Figure 25
from FE21 to FE1F.
with new timing diagrams.
description, added two
139