STVM100DS6F STMicroelectronics, STVM100DS6F Datasheet - Page 9

• Manufacturer Part Number: STVM100DS6F
• Description: IC I2C LCD VCOM CALIBRATR 8TSSOP
• Manufacturer: STMicroelectronics
• Type: Calibratorr

Specifications of STVM100DS6F

• Applications: TFT-LCD Panels: VCOM Driver
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-9082-2; STVM100DS6F

STVM100
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low
level signal put on the bus by the receiver, whereas the master generates an extra
acknowledge-related clock pulse (see
obliged to generate an acknowledge signal after the reception of each byte that has been
clocked out of the slave transmitter.
The device that acknowledges transmissions has to pull down the SDA line during the
acknowledge clock pulse in such a way, that the SDA line is a stable low during the high
period of the acknowledge-related clock pulse. The setup and hold times must be taken into
account. A master receiver must signal an end of transmitted data to the slave transmitter
by not generating an acknowledge on the last byte that has been clocked out of the slave. In
this case, the transmitter must leave the data line high to enable the master to generate the
stop condition.
Figure 6.
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
Acknowledgement sequence
START
MSB
1
Doc ID 13236 Rev 7
Figure
6). A slave receiver which is addressed is
2
LSB
8
ACKNOWLEDGEMENT
CLOCK PULSE FOR
Device operation
9
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