CX24118A-12Z,518 NXP Semiconductors, CX24118A-12Z,518 Datasheet - Page 18

• Manufacturer Part Number: CX24118A-12Z,518
• Description: IC SATELLITE TUNER DGTL 36HVQFN
• Manufacturer: NXP Semiconductors
• Type: Satellite Tunerr

Specifications of CX24118A-12Z,518

• Package / Case: 36-VQFN Exposed Pad, 36-HVQFN, 36-SQFN, 36-DHVQFN
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Bus Type: I2C
• Maximum Agc: 90 dB (Typ)
• Maximum Frequency: 2175 MHz
• Minimum Frequency: 925 MHz
• Mounting Style: SMD/SMT
• Function: Satellite
• Noise Figure: 10 dB
• Operating Supply Voltage: 3.3 V
• Supply Voltage (min): 3.13 V
• Supply Voltage (max): 3.47 V
• Minimum Operating Temperature: 0 C
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287217518

NXP Semiconductors
Figure 3.
2.5
CX24118A_N_2
Product data sheet
(1)
(2)
(3)
The LO divider is changed to
to 2175 MHz.
The PLL frequency divider is changed across the frequency band to optimize phase noise while keeping the value of
PLLInDiv[8:0] within its usable range of 65-511d.
This reference divider break-point is set at 37.5*Fxtal. For a 40 MHz Xtal, this value is 1500 MHz.
Crystal Oscillator and Reference Clock
Recommended Divider Settings vs. Frequency When Using 40 MHz Crystal
PLLRefDiv
LODivSel
÷ 4
÷ 2
÷ 2
÷ 1
(1)
(2)
925
The crystal oscillator should be used with a 40 MHz or 40.444 MHz third-overtone crystal. It
generates the reference frequency for the fractional synthesizer and provides the clock for
the rest of the system. It is also divided and buffered to produce an external clock that can be
used as a clock signal for the demodulator. Register bit OutRefDiv (0x02[2]) sets the
frequency of the reference clock output at pin CKREF_OUT so that when OUTRefDiv = 0, a
4.
Calculate the fractional divider PLLFracDiv[17:0].
PLLFracDiv[17:0] = Round [2
• To avoid fractional spurs, the fractional divider should not produce VCO
• When the requested frequency is within 250 kHz of the frequency generated by
• When the requested frequency is within 125 kHz of the frequency generated by
1165
÷
4 below 1165 MHz in order to keep the VCO frequency out of the input frequency range of 925
frequencies within 250 kHz or 125 kHz of the frequencies generated by
PLLFracDiv[17:0] = 0.0 or 0.5 respectively.
PLLFracDiv[17:0] = 0.0, the PLL should be put into integer mode. Integer mode is
enabled by setting register bit DSMByp (0x10[6]) to 1.
PLLFracDiv[17:0] = 0.5, the closest fractional value outside of the keep-out range
should be used.
Rev. 02 — 8 September 2009
f (MHz)
18
x (N
divider
- PLLIntDiv[8:0] - 32)]
Chapter 2: Functional Descriptions
1500
(3)
CX24118A
© NXP B.V. 2009. All rights reserved.
REN_003
2175
18