CX24118A-12Z,518 NXP Semiconductors, CX24118A-12Z,518 Datasheet - Page 37

• Manufacturer Part Number: CX24118A-12Z,518
• Description: IC SATELLITE TUNER DGTL 36HVQFN
• Manufacturer: NXP Semiconductors
• Type: Satellite Tunerr

Specifications of CX24118A-12Z,518

• Package / Case: 36-VQFN Exposed Pad, 36-HVQFN, 36-SQFN, 36-DHVQFN
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Bus Type: I2C
• Maximum Agc: 90 dB (Typ)
• Maximum Frequency: 2175 MHz
• Minimum Frequency: 925 MHz
• Mounting Style: SMD/SMT
• Function: Satellite
• Noise Figure: 10 dB
• Operating Supply Voltage: 3.3 V
• Supply Voltage (min): 3.13 V
• Supply Voltage (max): 3.47 V
• Minimum Operating Temperature: 0 C
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287217518

4.1
4.2
4.2.1
4.2.2
CX24118A_N_2
Product data sheet
Thermal Recommendations
Sleep Mode Procedures
Changing from Normal Operation to Sleep Mode
Changing from Sleep Mode to Normal Operation
The CX24118A uses a thermally enhanced QFN package with an exposed paddle
underneath the device to dissipate heat. The exposed paddle is soldered directly to exposed
PCB ground on the top layer of the board. Thermal vias then connect the top PCB layer to
the other board layers. The more layers that are used, the better the thermal properties of the
chip will be.
Table 8.
To change the tuner from normal operation to sleep mode, use the following procedure:
To change the tuner from sleep mode to normal operation, use the following procedure:
Number of PCB layers
Numbers of thermal vias
Thermal via spacing
Solder mask opening under exposed
paddle
Metallization land pattern
Via diameter
FOOTNOTES:
(1)
(2)
CX24118A
Chapter 4: Application Information
Rev. 02 — 8 September 2009
1.
2.
3.
1.
2.
3.
As many of the layers should be grounded and connected to the thermal vias as possible.
Same as the package exposed paddle. The area outside the solder mask opening to the pin pads
should be covered with solder mask.
Set register field TUNAutoEn[1:0] (0x14[7:6]) to 01b.
Set register field VCOSel[5:0] (0x18[7] and 0x18[5:0]) to 0.
Set the system enable bits (0x21[5:0]) to 0x00.
Set register field TUNAutoEn[1:0] (0x14[7:6]) to 01b.
Set the system enable bits (0x21[5:0]) to 0x3F.
Restart the tuning system by setting TUNReset to 1.
(2)
Parameter
Table 8
Thermal Recommendations
(1)
lists the CX24118A thermal layout recommendations.
Rev. 02 — 8 September 2009
2 or 4
16 (4x4 square matrix)
3.7 x 3.7 mm
3.7 x 3.7 mm
0.33 mm drill-hole size with 1 oz copper plating.
0.85 mm from center to center
Recommendations
Product data sheet
© NXP B.V. 2009. All rights reserved.
37