CX24118A-12Z,518 NXP Semiconductors, CX24118A-12Z,518 Datasheet - Page 29

• Manufacturer Part Number: CX24118A-12Z,518
• Description: IC SATELLITE TUNER DGTL 36HVQFN
• Manufacturer: NXP Semiconductors
• Type: Satellite Tunerr

Specifications of CX24118A-12Z,518

• Package / Case: 36-VQFN Exposed Pad, 36-HVQFN, 36-SQFN, 36-DHVQFN
• Applications: Set-Top Boxes
• Mounting Type: Surface Mount
• Bus Type: I2C
• Maximum Agc: 90 dB (Typ)
• Maximum Frequency: 2175 MHz
• Minimum Frequency: 925 MHz
• Mounting Style: SMD/SMT
• Function: Satellite
• Noise Figure: 10 dB
• Operating Supply Voltage: 3.3 V
• Supply Voltage (min): 3.13 V
• Supply Voltage (max): 3.47 V
• Minimum Operating Temperature: 0 C
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935287217518

NXP Semiconductors
3.4
Register 00
Register 01
Register 02
Register 10
CX24118A_N_2
Product data sheet
Register (Hex)
CHPId[7:0]
CHPVer[7:0]
OUTRefDiv
PLLRefDiv
Register
Register
Register
(Hex)
(Hex)
(Hex)
00
01
02
10
Register Detail
POR
POR
POR
POR
43
03
00
00
DSMClkPol
This section provides the register detail.
Chip Identification Number.
The current chip ID is 0x23. Read only.
Chip Version Number.
The current chip version is 0x03. Read only.
Output Reference Divider.
0
1 =
PLL Reference Divider.
0 = ÷1.
1 = ÷2.
This bit selects the reference clock divider for the CKREF_OUT pin. See
This bit selects the divider for the tuner synthesizer reference frequency.
D7
D7
D7
D7
NOTE:
NOTE:
=
÷2.
÷1.
DSMByp
D6
D6
D6
D6
POR refers to power-on reset value.
All bits in the registers are Read/Write unless indicated otherwise in the bit
description.
Rev. 02 — 8 September 2009
Reserved
D5
D5
D5
D5
CPMan[1:0]
Chapter 3: Serial Programming Interface and Registers
D4
D4
D4
D4
CHP
CHPId[7:0]
Ver[7:0]
D3
D3
D3
D3
CPDVal[1:0]
OUTRefDiv
Section 2.5
D2
D2
D2
D2
for more detail.
PLLRefDiv
TUNLD
D1
D1
D1
D1
CX24118A
© NXP B.V. 2009. All rights reserved.
Reserved
CPSel
D0
D0
D0
D0
29