TMPM380FYDFG Toshiba, TMPM380FYDFG Datasheet - Page 451
TMPM380FYDFG
Manufacturer Part Number
TMPM380FYDFG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM380FWDFG.pdf
(700 pages)
Specifications of TMPM380FYDFG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
16K
Number Of Pins
100
Package
QFP(14×20)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
2
I2c/sio (ch)
2
Uart/sio (ch)
5
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
18
16-bit Timer / Counter
8
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
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15 Serial Bus Interface (I2C/SIO)
15.6.2 Generating the Start Condition and a Slave Address
Settings in main routine
Example of INTSBIn interrupt routine
Clears the interrupt request.
Processing
End of interrupt
Reg.
Reg.
if Reg.
Then
SBInCR1 ← X X X 1 0 X X X
SBInDBR ← X X X X X X X X
SBInCR2 ← 1 1 1 1 1 0 0 0
Master mode
In the master mode, the following steps are required to generate the start condition
and a slave address.
First, ensure that the bus is free (<BB> = “0”). Then, write “1” to SBInCR1 <ACK> to
select the acknowledgment mode. Write to SBInDBR a slave address and a direction
bit to be transmitted.
When <BB> = “0,” writing “1111” to SBInCR2 <MST, TRX, BB, PIN> generates the
start condition on the bus. Following the start condition, the SBI generates nine clocks
from the SCL pin. The SBI outputs the slave address and the direction bit specified at
SBInDBR with the first eight clocks, and releases the SDA line in the ninth clock to
receive an acknowledgment signal from the slave device.
The INTSBIn interrupt request is generated on the falling of the ninth clock, and <PIN>
is cleared to ”0.” In the master mode, the SBI holds the SCL line at the “L” level while
<PIN> is “0.” <TRX> changes its value according to the transmitted direction bit at
generation of the INTSBIn interrupt request, provided that an acknowledgment signal
has been returned from the slave device.
≠ 0x00
← SBISR
← Reg. e 0x20
7 6 5 4 3 2 1 0
TMPM380/M382 - 22 / 41 -
Ensures that the bus is free.
Selects the acknowledgement mode.
Specifies the desired slave address and direction.
Generates the start condition.
TMPM380/M382
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