TMPM380FYDFG Toshiba, TMPM380FYDFG Datasheet - Page 70
TMPM380FYDFG
Manufacturer Part Number
TMPM380FYDFG
Description
Manufacturer
Toshiba
Datasheet
1.TMPM380FWDFG.pdf
(700 pages)
Specifications of TMPM380FYDFG
Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
256K
Rom Type
Flash
Ram (kbytes)
16K
Number Of Pins
100
Package
QFP(14×20)
Vcc
5V
Cpu Mhz
40
Ssp (ch) Spi
2
I2c/sio (ch)
2
Uart/sio (ch)
5
Usb
-
Can
-
Ethernet
-
External Bus Interface
N
Cs/wait Controller (ch)
-
Dma Controller
2
10-bit Da Converter
-
10-bit Ad Converter
-
12-bit Ad Converter
18
16-bit Timer / Counter
8
Motor / Igbt Control
Y
Real Time Clock
1
Watchdog Timer
Y
Osc Freq Detect
Y
Clock Gear
Y
Low-power Hold Function
-
Remote Control Interface
Y
Hardware Cec Controller
-
Comparators
-
Low-voltage Detector
Y
Etm Hardware Trace
2-bit
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recognize an interrupt signal as an interrupt factor when it is changed from “L” to “H”. A signal directly
sent from the peripheral IP to the CPU is configured to output the “H” pulse as an interrupt request.
active level setting for Clock Generator is selectable from “H” level, “L” level, rising edge or falling edge.
function as the standby clearing factor. However, inputting the “H” pulse or the “H” level signal is required
so that the CPU can detect it as an interrupt factor.
7.5.1.5 Active Level
The active level indicates which change in signal of an interrupt factor triggers an interrupt. The CPU
Only interrupt request from external pin have the option as the interrupt to clear the standby mode. The
If the interrupt is used for clearing the standby mode, setting the clock generator register is required.
The interrupt detected by the clock generator is notified to the CPU as “H” level signal.
An interrupt from the external pin can be used without setting the clock generator in case it does not
i.e. Enable the CGIMCGx<INTxEN> bit and specify the active level in the CGIMCGx<EMCG2:0> bits.
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