TMP86xy45UG Toshiba, TMP86xy45UG Datasheet - Page 105

• Manufacturer Part Number: TMP86xy45UG
• Manufacturer: Toshiba

Specifications of TMP86xy45UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 8
• Ram Size: 256
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: -
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: -
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 2.7 to 5.5

9.3 Function
SIOSR<TXERR>
SIOTDB
SIOCR1
<SIOINH>
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK
SO pin
SIOSR<TXF>
INTSIO
interrupt
request
9.3.3.2
pin
Writing transmit
data A
Receive mode
(1)
(2)
The receive mode is selected by writing “01B” to SIOCR<SIOM>.
SIOCR1<SCK>. Transfer direction is selected by using SIOCR1<SIODIR>.
SCK
direction of the bit specified by SBIDIR<SIODIR>.
clock falling edge.
rupt request is generated and SIOSR<RXF> is set to “1”
when the all of the 8-bit data has been received. Automatic-wait function is released by reading a
received data from SIORDB. Then, receive operation is restarted after maximum 1-cycle of serial
clock.
SIORDB, before the next data shift-in operation is finished.
Starting the receive operation
Receive mode is selected by setting “01” to SIOCR1<SIOM>. Serial clock is selected by using
After SIOCR1<SIOS> is set to “1”, SIOSR<SIOF> is set synchronously to “1” the falling edge of
Synchronizing with the
SIOSR<SEF> is kept in high level, between the first clock falling edge of
When 8-bit data is received, the data is transferred to SIORDB from shift register. INTSIO inter-
Note: In internal clock operation, when the SIOCR1<SIOS> is set to "1", the serial clock is generated
During the receive operation
The SIOSR<RXF> is cleared to “0” by reading a data from SIORDB.
In the internal clock operation, the serial clock stops to “H” level by an automatic-wait function
In external clock operation, after SIOSR<RXF> is set to “1”, the received data must be read from
Figure 9-9 Example of Transmit Error Processingme
A
pin.
from
A7 A6
Writing transmit
data B
SCK
Start shift
operation
pin after maximum 1-cycle of serial clock frequency.
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
B
SCK
pin's rising edge, the data is received sequentially from SI pin with the
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Start shift
operation
Start shift
operation
SCK
Unknown
TMP86C845UG
pin and eighth