TMP86xy45UG Toshiba, TMP86xy45UG Datasheet - Page 27

• Manufacturer Part Number: TMP86xy45UG
• Manufacturer: Toshiba

Specifications of TMP86xy45UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 8
• Ram Size: 256
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: -
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: -
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 2.7 to 5.5

2.2 System Clock Controller
2.2.4 Operating Mode Control
2.2.4.1
Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.
Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt.
SSTOPH:
PINT5:
SINT5:
The
started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.
selected with the SYSCR1<RELM>.
STOP mode
(1)
STOP mode is controlled by the system control register 1, the
STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be
Note 1: During STOP period (from start of STOP mode to end of warm up), due to changes in the external
STOP
backup when the main power supply is cut off and long term battery backup.
mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode
in the level-sensitive release mode, it is necessary for the program to first confirm that the
input is low. The following two methods can be used for confirmation.
1. Oscillations are turned off, and all internal operations are halted.
2. The data memory, registers, the program status word and port output latches are all held in the
3. The prescaler and the divider of the timing generator are cleared to “0”.
4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])
Level-sensitive release mode (RELM = “1”)
In this mode, STOP mode is released by setting the
Even if an instruction for starting STOP mode is executed while
LD
TEST
JRS
DI
SET
TEST
JRS
LD
DI
SET
RETI
status in effect before STOP mode was entered.
which started STOP mode.
interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately
after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before
enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.
pin is also used both as a port P20 and an
1. Testing a port.
2. Using an external interrupt input
(P2PRD). 0
(SYSCR1), 01010000B
F, SSTOPH
(SYSCR1). 7
(P2PRD). 0
F, SINT5
(SYSCR1), 01010000B
(SYSCR1). 7
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; Sets up the level-sensitive release mode
; Wait until the
; IMF ← 0
; Sets up the level-sensitive release mode.
; IMF ← 0
; Starts STOP mode
; To reject noise, STOP mode does not start if
; Starts STOP mode
port P20 is at high
INT5
(
INT5
INT5
STOP
pin input goes low level
STOP
(external interrupt input 5) pin. STOP mode is
is a falling edge-sensitive input).
STOP
pin high. This mode is used for capacitor
pin input.
STOP
pin input is high, STOP
TMP86C845UG
STOP
pin