TMP86xy45UG Toshiba, TMP86xy45UG Datasheet - Page 8

• Manufacturer Part Number: TMP86xy45UG
• Manufacturer: Toshiba

Specifications of TMP86xy45UG

• Package: QFP44
• Rom Types (m=mask,p=otp,f=flash): M/P
• Rom Size: 8
• Ram Size: 256
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: -
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: -
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 35
• Power Supply (v): 2.7 to 5.5

2. Operational Description
3. Interrupt Control Circuit
TMP86C845UG
1.1
1.2
1.3
1.4
2.1
2.2
2.3
3.1
3.2
3.3
3.4
2.1.1
2.1.2
2.1.3
2.2.1
2.2.2
2.2.3
2.2.4
2.3.1
2.3.2
2.3.3
2.3.4
3.2.1
3.2.2
3.4.1
3.4.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2.2.1
2.2.2.2
2.2.3.1
2.2.3.2
2.2.3.3
2.2.4.1
2.2.4.2
2.2.4.3
2.2.4.4
Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.2.1
Memory Address Map............................................................................................................................... 7
Program Memory (MaskROM).................................................................................................................. 7
Data Memory (RAM) ................................................................................................................................. 7
Clock Generator........................................................................................................................................ 8
Timing Generator .................................................................................................................................... 10
Operation Mode Control Circuit .............................................................................................................. 11
Operating Mode Control ......................................................................................................................... 16
External Reset Input ............................................................................................................................... 29
Address trap reset .................................................................................................................................. 30
Watchdog timer reset.............................................................................................................................. 30
System clock reset.................................................................................................................................. 30
Interrupt master enable flag (IMF) .......................................................................................................... 34
Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 34
Interrupt acceptance processing is packaged as follows........................................................................ 37
Saving/restoring general-purpose registers ............................................................................................ 38
Configuration of timing generator
Machine cycle
Single-clock mode
Dual-clock mode
STOP mode
STOP mode
IDLE1/2 mode and SLEEP1/2 mode
IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)
SLOW mode
Using PUSH and POP instructions
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