TMP86xy46NG Toshiba, TMP86xy46NG Datasheet - Page 58

• Manufacturer Part Number: TMP86xy46NG
• Manufacturer: Toshiba

Specifications of TMP86xy46NG

• Package: SDIP42
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 8/16/32
• Ram Size: 512/512/1K
• Driver Led: 19
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: -
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 8
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 1
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 33
• Power Supply (v): 4.5 to 5.5

5. I/O Ports
input data should be externally held until the input data is read from outside or reading should be performed several
timer before processing. Figure 5-1 shows input/output timing examples.
This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the
program.
port.
The TMP86PM46NG have 5 parallel input/output ports (33 pins) as follows.
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external
External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction.
Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O
Note: The positions of the read and write cycles may vary, depending on the instruction.
Instruction execution cycle
Instruction execution cycle
Port P0
Port P1
Port P2
Port P3
Port P4
Output strobe
8-bit I/O port
6-bit I/O port
3-bit I/O port
8-bit I/O port
8-bit I/O port
Data output
Input strobe
Primary Function
Data input
Figure 5-1 Input/Output Timing (Example)
External interrupt input, serial and timer/counter input/output.
External interrupt input, and timer/counter input/output.
Analog input, and STOP mode release signal input.
Low-frequency resonator connections, external interrupt input, and STOP mode
release signal input.
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3
Fetch cycle
Fetch cycle
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Ex: LD A, (x)
Ex: LD (x), A
(b) Output timing
(a) Input timing
Fetch cycle
Fetch cycle
Secondary Functions
Old
Read cycle
Write cycle
New
TMP86PM46NG