TMP86xy46NG Toshiba, TMP86xy46NG Datasheet - Page 74
TMP86xy46NG
Manufacturer Part Number
TMP86xy46NG
Description
Manufacturer
Toshiba
Datasheet
1.TMP86XY46NG.pdf
(171 pages)
Specifications of TMP86xy46NG
Package
SDIP42
Rom Types (m=mask,p=otp,f=flash)
M/P/F
Rom Size
8/16/32
Ram Size
512/512/1K
Driver Led
19
Driver Lcd
-
Spi/sio Channels
1
Uart/sio Channels
1
I2c/sio Channels
-
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
8
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
1
Timer Counter 8-bit Channel
2
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
-
Number Of I/o Ports
33
Power Supply (v)
4.5 to 5.5
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7.3.4 Address Trap Reset
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”) or the SFR
area, address trap reset will be generated.
hardware is reset. The reset time is maximum 24/fc [s] (1.5 µs @ fc = 16.0 MHz).
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an
When an address trap reset request is generated, the
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre-
quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura-
cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
Page 63
RESET
pin outputs a low-level signal and the internal
TMP86PM46NG
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