FAN21SV04 Fairchild Semiconductor, FAN21SV04 Datasheet
FAN21SV04
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FAN21SV04 Summary of contents
Page 1
... The FAN21SV04 can be configured to drive multiple slave devices OR synchronize to an external system clock. In slave mode, FAN21SV04 may be set free-running in the absence of a master clock signal. External frequency, and current-limit features allow for design optimization and flexibility ...
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... Figure 1. Typical Application as Master at V Block Diagram VIN_Reg Reg 5V_Reg ILIM Int ref COMP Error Amplifier REF CLK OSC RAMP EN GEN RAMP © 2009 Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 VIN Boot Diode 5V_Reg VIN_Reg C5 RAMP PWM + DRIVER EN ILIM AGND COMP 5V Current Limit I ...
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... Ramp Amplitude. A resistor (R 25 RAMP amplitude and also provides voltage feedforward functionality. © 2009 Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 BOOT ) from this pin to AGND can be used to program the current- ILIM ) connected from this pin to VIN sets the internal ramp RAMP ...
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... Note: 1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 38. Actual results are dependent upon mounting method and surface related to the design. © 2009 Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 Conditions Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 ...
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... Output Voltage Swing (V ) COMP Output Current, Sourcing Output Current, Sinking FB Bias Current Note: 2. Specifications guaranteed by design and characterization; not production tested. © 2009 Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 Conditions V =12V, 5V_Reg Open, CLK Open =500KHz, No Load SW EN=High, 5V_Reg Open, CLK Open, f ...
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... Over-Temperature Hysteresis Over-Voltage Threshold Under-Voltage Shutdown Fault-Discharge Threshold Fault-Discharge Hysteresis Note: 3. Delay times are not tested in production. Guaranteed by design. © 2009 Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 (Continued) Conditions VIN_Reg >6.5V Auto-Restart Mode, VIN_Reg>6.5V FB < Consecutive Clock Cycles REF FB > Consecutive Clock Cycles ...
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... R T Figure 6. Frequency vs. R 1.60 1.40 1.20 1.00 0.80 0.60 -50 0 Temperature ( Figure 8. R vs. Temperature, Normalized DS (5V_Reg=V GS © 2009 Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 1.20 1.10 1.00 0.90 0.80 50 100 150 - vs. Temperature, Figure 5. Reference Bias Current (I FB 1.02 1.01 1.00 0.99 0.98 -50 80 100 120 140 (K ) (Master) Figure 7 ...
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... Application Circuit Figure 10. Single-Supply Application Circuit: 1.8V Figure 11. Single -Supply Application Circuit: 1.2 V © 2009 Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 FAN21SV04 , 500KHz, Master, 8V – 20V Input OUT FAN21SV04 , 500KHz, Master 8V – 20V Input OUT 8 www.fairchildsemi.com ...
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... OUT 0.5 1 1.5 2 Load (A) Figure 16. 1.2 V Efficiency, 500KHz (Figure 11) OUT Note: 4. Circuit values for this configuration change in Figure 10. © 2009 Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 =12V 1.8V_Eff 8-20V_500kHz 12V 75 16V 20V 70 0 2.5 3 3.5 4 vs. Load Figure 13. 3 ...
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... Figure 19. 1 12V_HS 12V_LS 20 24V_HS 24V_LS 10 0 2 Figure 21. Peak Case Temperature Over MOSFET (5) Recommended FAN21SV04 Safe Operating Area curves for 70 Deg 1.8V_Eff 12V Input 300kHz 400kHz 3 500kHz 2 600kHz 2.5 3 3.5 4 Figure 23. Typical Output Operating Area Based on SW ...
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... EN, 1V/div CLK, 5V/div PGOOD, 5V/div Figure 24. CLK and 1V/div OUT SW, 10V/div Figure 26. Startup on Pre-Bias Figure 28. Shutdown, 1A Load © 2009 Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 (Continued) =12V unless otherwise specified 1V/div OUT at Startup Figure 25. Transient Response, 2-4A Load OUT CLK, 5V/div V ...
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... If the parallel combination of R1 and R internal SS ramp is not released and the regulator does not start. Enable FAN21SV04 has an internal pull-up to the enable (EN) pin so that the IC is enabled once VIN_Reg exceeds the UVLO threshold. Connecting a small capacitor across EN and AGND delays the rate of voltage rise on the EN pin ...
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... After a fault, the EN pin is discharged with 1µA current pull-down to a 1.1V threshold before the internal 800k pull-up is restored. A new soft-start cycle begins when EN charges above 1.35V. Depending on the external circuit, the FAN21SV04 can be configured to remain latched off or automatically restart after a fault, as listed in Table 1. Table 1. ...
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... T Setting the Current Limit There are two levels of current-limit thresholds in FAN21SV04. The first level of protection is through an internal default limit set at the factory to provide cycle- by-cycle current limit and prevent output current (2) beyond normal levels. The second level of protection is set at the ILIM pin by connecting a resistor (R between ILIM and AGND ...
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... Free-running capability in the absence of system clock or, if the master is disabled/faulted, the slaves can continue to regulate at a lower frequency The FAN21SV04 master outputs an 85ns-wide clock (CLK) signal, delayed 180 This feature allows out-of-phase operation for the slaves, thereby reducing the input capacitance requirements when more than one converter is operating on the same input supply ...
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... Figure 37. Slaves with 180 Since the synchronizing circuit utilizes a narrow reset pulse, the actual phase delay is slightly more than 180 The FAN21SV04 is not intended for use in single-output, multi-phase regulator applications. © 2009 Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 ...
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... Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 2X ALL VALUES TYPICAL EXCEPT WHERE NOTED A) DIMENSIONS ARE IN MILLIMETERS. ...
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... Fairchild Semiconductor Corporation FAN21SV04 • Rev. 1.0.2 18 www.fairchildsemi.com ...