FAN21SV04 Fairchild Semiconductor, FAN21SV04 Datasheet - Page 15

• Manufacturer Part Number: FAN21SV04
• Description: This part is covered in Fairchild's href="http://www
• Manufacturer: Fairchild Semiconductor

© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.2
R
The ILIM pin can source a 10µA current that can be
used to establish a lower, temperature-dependent,
current-limit threshold by connecting an external resistor
(R
equation:
where:
I
V
V
R
f
After 16 consecutive pulse-by-pulse current-limit cycles,
the fault latch is set and the regulator shuts down. Cycling
VIN_Reg or EN restores operation after a normal soft-
start cycle (refer to the Auto-Restart section).
The over-current protection fault latch is active during
the soft-start cycle. Use a 1% resistor for R
given R
varies slightly in an inverse relationship to V
not connected, the IC uses the internal default current-
limit threshold.
Loop Compensation
The control loop is compensated using a feedback
network around the error amplifier. Figure 34 shows a
complete
compensation eliminates R3 and C3.
OUT
ILIM
OUT
IN
RAMP
ILIM
K (

) to AGND. R
)
= Full load current in Amps;
= Set output voltage;
= Input voltage;
= Ramp resistor used in K; and
= Selected switching frequency in KHz.

RAMP
95
Figure 34. Compensation Network

15
Type-3
1 .
and R

Figure 33. ILIM Network
I
OUT

ILIM
V (
ILIM
compensation
IN
R (

can be approximated with the
setting, the current-limit point
. 1
RAMP
) 8

V

OUT
) 2


V
. 3
IN
33

f
network.

10
6
I
N. If R
ILIM
. For a
Type-2
ILIM
(6)
is
15
Since the FAN21SV04 employs summing current-mode
architecture, Type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, Type-3 compensation may be required.
R
in V
increases as V
to compensate the loop. For low-input-voltage-range
designs (3V to 8V), R
component values are different as compared to designs
with V
Master / Slave Configuration
When first enabled, the IC determines if it is configured
as a master or slave for synchronization, depending on
how R
Table 2.
Slaves free-run in the absence of an external clock
signal input when R
regulation to be maintained. It is not recommended to
leave R
noise pick up on the clock pin.
Slave free-running frequency should be set at least 25%
lower than the incoming synchronizing pulse frequency.
Maximum
recommended to be below 600KHz.
Synchronization
The
FAN21SV04 also provides the following features for
maximum flexibility.




The FAN21SV04 master outputs an 85ns-wide clock
(CLK) signal, delayed 180
This feature allows out-of-phase operation for the slaves,
thereby reducing the input capacitance requirements
when more than one converter is operating on the same
input supply. The leading SW-node edge is delayed
~40ns from the rising PWM signal.
On a slave, synchronization is rising-edge triggered. The
CLK input pin has a 1.8V threshold and a 200µA current
source pull-up.
RAMP
5V_Reg
R
GND
IN
Synchronization to an external system clock
Multiple FAN21SV04s can be synchronized to a
single master or system clock
Independently programmable phase adjustment for
one or multiple slaves
Free-running capability in the absence of system
clock or, if the master is disabled/faulted, the slaves
can continue to regulate at a lower frequency
T
. With a fixed R
IN
T
synchronization
provides feedforward compensation for changes
to:
is connected.
between 8V and 24V.
T
open when running in Slave Mode to avoid
Master / Slave Configuration
synchronizing
IN
Master / Slave
Master
Slave, free-running
is reduced, which can make it difficult
T
is connected to 5V_Reg, allowing
RAMP
method
RAMP
o
from its leading PWM edge.
value, the modulator gain
clock
and the compensation
employed
frequency
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CLK Pin
Output
Input
by
the
is