FAN21SV04 Fairchild Semiconductor, FAN21SV04 Datasheet - Page 13

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FAN21SV04

Manufacturer Part Number
FAN21SV04
Description
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Manufacturer
Fairchild Semiconductor
Datasheet

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FAN21SV04 • Rev. 1.0.2
Startup on Pre-Bias
The regulator does not allow the low-side MOSFET to
operate in full synchronous mode until SS reaches 95%
of V
on a pre-biased output and ensures that output is not
discharged during the soft-start cycle.
Protections
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, and under-
voltage conditions.
Under-Voltage Protection
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This protection is not active until
the internal SS ramp reaches 1.0V during soft-start.
Over-Voltage Protection
If FB exceeds 115%
cycles, the fault latch is set and shutdown occurs.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
The OV/UV fault conditions are not allowed to set the
fault latch during soft-start. They are active only after
T1.0 (see Figure 31).
Figure 31. Typical Soft-Start Timing Diagram
REF
(~0.76V). This enables the regulator to startup
V
REF
for two consecutive clock
13
Over-Temperature Protection
The chip incorporates an over-temperature protection
circuit that sets the fault latch when a die temperature of
about 155°C is reached. The IC is allowed to restart
when the die temperature falls below 125°C.
Auto-Restart
After a fault, the EN pin is discharged with 1µA current
pull-down to a 1.1V threshold before the internal 800k
pull-up is restored. A new soft-start cycle begins when
EN charges above 1.35V.
Depending on the external circuit, the FAN21SV04 can
be configured to remain latched off or automatically
restart after a fault, as listed in Table 1.
Table 1.
With EN left open, restart is immediate.
If auto-restart is not desired, tie the EN pin HIGH with a
logic gate to keep the 1µA current sink from discharging
EN to 1.1V. Figure 32 shows one method to pull up EN
to V
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW when
V
The
Specifications section. PGOOD does not assert HIGH
until soft start is complete (T1.0) (see Figure 31).
EN Pin
Pull to GND
Connected to
5V_Reg with
100K
Open
Cap to GND
OUT
Figure 32.
CC
is out of regulation, as measured at the FB pin.
thresholds
for a latch configuration.
Fault / Restart Configurations
Enable Control with Latch Option
Controller / Restart State
OFF (Disabled)
No Restart – Latched OFF
Immediate Restart After Fault
New Soft-Start Cycle After EN is
HIGH (Auto Restart Mode)
are
specified
in
the
www.fairchildsemi.com
Electrical

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