FAN21SV04 Fairchild Semiconductor, FAN21SV04 Datasheet - Page 16

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FAN21SV04

Manufacturer Part Number
FAN21SV04
Description
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Manufacturer
Fairchild Semiconductor
Datasheet

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FAN21SV04 • Rev. 1.0.2
In Master Mode, the clock signals go out after power-
good signal asserts HIGH. Likewise, in Slave Mode,
synchronization to an external clock signal occurs after
the power-good signal goes HIGH. Until then, the
converter operates in free-run mode.
One or more slaves can be connected directly to a
master or system clock to achieve a 180
Since the synchronizing circuit utilizes a narrow reset
pulse, the actual phase delay is slightly more than 180
The FAN21SV04 is not intended for use in single-output,
multi-phase regulator applications.
Figure 35. Synchronization Timing Diagram
Figure 36. Slave-CLK-Input Block Diagram
Figure 37. Slaves with 180
o
Phase Shift
o
phase shift.
o
.
16
PCB Layout
Good PCB layout and careful attention to temperature
rise is essential for reliable operation of the regulator.
Four-layer PCB with two-ounce copper on the top and
bottom side and thermal vias connecting the layers is
recommended. Keep power traces wide and short to
minimize losses and ringing. Do not connect AGND to
PGND below the IC. Connect AGND pin to PGND at the
output OR to the PGND plane.
V
OUT
Figure 38. Recommended PCB Layout
SW
PGND
V
IN
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PGND

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