FAN21SV04 Fairchild Semiconductor, FAN21SV04 Datasheet - Page 3

• Manufacturer Part Number: FAN21SV04
• Description: This part is covered in Fairchild's href="http://www
• Manufacturer: Fairchild Semiconductor

© 2009 Fairchild Semiconductor Corporation
FAN21SV04 • Rev. 1.0.2
Pin Configuration
Pad / Pin Definitions
Pad / Pin
P3, 21-23
P1, 6-12
P2, 3-5
13
14
15
16
17
18
19
20
24
25
1
2
VIN_Reg
PGOOD
5V_Reg
Name
COMP
PGND
BOOT
AGND
RAMP
ILIM
CLK
SW
VIN
EN
FB
R
T
Description
Switching Node. Junction of high-side and low-side MOSFETs.
Power Conversion Input Voltage. Connect to the main input power source.
Power Ground. Power return and Q2 source.
High-Side Drive BOOT Voltage. Connect through capacitor (C
internal synchronous bootstrap diode to recharge the capacitor on this pin to 5V_Reg when
SW is LOW.
Regulator Input Voltage. Input voltage to the internal regulator. Connect to input voltage
>6.5V with 10resistor and a 1µF bypass capacitor at the pin (see Figure 10).
Power-Good. An open-drain output that pulls LOW when the voltage on the FB pin is
outside the specified limits. PGOOD does not assert HIGH until the fault latch is enabled
(see Figure 31).
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched-fault condition. This input has an internal pull-up. When a latched
fault occurs, EN is discharged by a current sink.
5V Regulator Output. Internal regulator output that provides power for the IC’s logic and
analog circuitry. This pin should be connected to AGND through a >2.2µf X5R/X7R
capacitor.
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
Current Limit. A resistor (R
limit trip threshold lower than the internal default setting.
Switching Frequency and Master/Slave Set. Connecting a resistor (R
switching frequency and configures the CLK pin as an output (master). Tying this pin to
5V_Reg through a resistor configures the CLK signal as an input (slave) and establishes the
free-running switching frequency.
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
Compensation. Error amplifier output. Connect the external compensation network
between this pin and FB.
Clock. Bi-directional signal pin, depending on master/slave configuration. When configured
as a master, this pin represents the clock output that connects directly to the slave(s) for
synchronizing with 180° phase shift.
Ramp Amplitude. A resistor (R
amplitude and also provides voltage feedforward functionality.
Figure 3. MLP 5x6mm Pin Configuration (Bottom View)
ILIM
) from this pin to AGND can be used to program the current-
RAMP
3
) connected from this pin to VIN sets the internal ramp
BOOT
) to SW. The IC has an
T
) to AGND sets the
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