74AUP2G17GW,125 NXP Semiconductors, 74AUP2G17GW,125 Datasheet

IC BUFF DL SCHM TRG L PWR SC88

74AUP2G17GW,125

Manufacturer Part Number
74AUP2G17GW,125
Description
IC BUFF DL SCHM TRG L PWR SC88
Manufacturer
NXP Semiconductors
Series
74AUPr
Datasheet

Specifications of 74AUP2G17GW,125

Package / Case
SC-70-6, SC-88, SOT-363
Logic Type
Schmitt Trigger - Buffer, Driver
Number Of Elements
2
Number Of Bits Per Element
1
Current - Output High, Low
4mA, 4mA
Voltage - Supply
0.8 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
AUP
Number Of Channels Per Chip
2
Polarity
Non-Inverting
Supply Voltage (max)
3.6 V
Supply Voltage (min)
0.8 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 4 mA
Input Bias Current (max)
0.5 uA
Low Level Output Current
4 mA
Minimum Operating Temperature
- 40 C
Propagation Delay Time
19 ns @ 1.1 V to 1.3 V or 11.2 ns @ 1.4 V to 1.6 V or 9.2 ns @ 1.65 V to 1.95 V or 7 ns @ 2.3 V to 2.7 V or 6.2 ns @ 3 V to 3.6 V
Number Of Lines (input / Output)
2 / 2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74AUP2G17GW-G
74AUP2G17GW-G
935279991125
1. General description
2. Features and benefits
The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
This device ensures a very low static and dynamic power consumption across the entire
V
This device is fully specified for partial power-down applications using I
The I
the device when it is powered down.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
hysteresis voltage V
CC
74AUP2G17
Low-power dual Schmitt trigger
Rev. 4 — 3 November 2010
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
Low static power consumption; I
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
I
Multiple package options
Specified from −40 °C to +85 °C and −40 °C to +125 °C
OFF
range from 0.8 V to 3.6 V.
OFF
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
circuitry provides partial Power-down mode operation
circuitry disables the output, preventing the damaging backflow current through
H
.
T+
and the negative voltage V
CC
= 0.9 μA (maximum)
CC
T−
is defined as the input
Product data sheet
OFF
.

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74AUP2G17GW,125 Summary of contents

Page 1

Low-power dual Schmitt trigger Rev. 4 — 3 November 2010 1. General description The 74AUP2G17 provides two Schmitt trigger buffers capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. This device ensures a ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74AUP2G17GW −40 °C to +125 °C 74AUP2G17GM −40 °C to +125 °C 74AUP2G17GF −40 °C to +125 °C 74AUP2G17GN −40 °C to +125 °C 74AUP2G17GS 4. Marking Table 2. Marking ...

Page 3

... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP2G17 GND 001aab674 Fig 4. Pin configuration SOT363 6.2 Pin description Table 3. Pin description Symbol Pin 1A 1 GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level. 74AUP2G17 Product data sheet 74AUP2G17 GND ...

Page 4

... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...

Page 5

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I power-off leakage current OFF ΔI additional power-off leakage OFF current I supply current CC ΔI additional supply current CC C input capacitance ...

Page 6

... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter ΔI additional power-off leakage OFF current I supply current CC ΔI additional supply current CC = −40 °C to +125 °C T amb V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current ...

Page 7

... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay nA to nY; see propagation delay nA to nY; see propagation delay nA to nY; see propagation delay nA to nY; see 74AUP2G17 Product data sheet Figure 8 ...

Page 8

... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions pF and power dissipation MHz capacitance [1] All typical values are measured at nominal V [ the same as t and t pd PLH PHL [ used to determine the dynamic power dissipation (P PD × ...

Page 9

... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 8. Test circuit for measuring switching times Table 10. ...

Page 10

... NXP Semiconductors Table 11. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Symbol Parameter Conditions V hysteresis voltage ( Figure Figure 14. Waveforms transfer characteristics T− Fig 9. Transfer characteristic 74AUP2G17 Product data sheet …continued Figure Min − see Figure 9, T− ...

Page 11

... NXP Semiconductors Fig 11. Typical transfer characteristics; V Fig 12. Typical transfer characteristics; V 74AUP2G17 Product data sheet 240 I CC (μA) 160 0.4 0.8 1 1200 I CC (μA) 800 400 0 0 1.0 2 All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 November 2010 ...

Page 12

... NXP Semiconductors 15. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula add P = additional power dissipation (μW); add f = input frequency (MHz input rise time (ns input fall time (ns ΔI CC(AV) Average ΔI (1) Positive-going edge ...

Page 13

... NXP Semiconductors 16. Package outline Plastic surface-mounted package; 6 leads y 6 pin 1 index DIMENSIONS (mm are the original dimensions UNIT max 1.1 0.30 0.25 mm 0.1 0.8 0.20 0.10 OUTLINE VERSION IEC SOT363 Fig 14. Package outline SOT363 (SC-88) 74AUP2G17 Product data sheet scale 2.2 1.35 2 ...

Page 14

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 15

... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 16 ...

Page 16

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 17

... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...

Page 18

... NXP Semiconductors 17. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 18. Revision history Table 13. Revision history Document ID Release date 74AUP2G17 v.4 20101103 • Modifications: Added type number 74AUP2G17GN (SOT1115/XSON6 package). ...

Page 19

... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

Page 20

... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 20. Contact information For more information, please visit: For sales office addresses, please send an email to: 74AUP2G17 Product data sheet 19 ...

Page 21

... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 13 Transfer characteristics ...

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