STPCC03 STMicroelectronics, STPCC03 Datasheet - Page 47

• Manufacturer Part Number: STPCC03
• Description: STPC CONSUMER-S DATASHEET- PC COMPATIBLE EMBEDDED MICROPROCESSOR
• Manufacturer: STMicroelectronics

6.3 Memory interface
6.3.1 Introduction
In order to achieve SDRAM memory interfaces
which work at clock frequencies of 100MHz and
above, careful consideration has to be given to the
timing of the interface with all the various electrical
and physical constraints taken into consideration.
The guidelines described below are related to
SDRAM components on DIMM modules. For ap-
plications where the memories are directly sol-
dered to the motherboard, the PCB should be laid
out such that the trace lengths fit within the con-
straints shown here. The traces could be slightly
longer since the extra routing on the DIMM PCB is
6.3.3 Board Layout Issues
The physical layout of the motherboard PCB as-
sumed in this presentation is as shown inFigure
6-10. Because all the memory interface signal
balls are located in the same region of the STPC
device it is possible to orientate the device to re-
duce the trace lengths. The worst case routing
length to the DIMM1 is estimated to be 100mm.
Solid power and ground planes are a must in order
to provide good return paths for the signals and to
reduce EMI and noise. Also there should be ample
high frequency decoupling between the power
Figure 6-9. Clock scheme
CONTROLLER
SDRAM
PLL
PLL
Issue 1.1 - October 16, 2000
MCLKO
MCLKI
MA[] + Control
MD[]
no longer present but it is then up to the user to
verify the timings.
6.3.2 SDRAM Clocking Scheme
The SDRAM Clocking Scheme deserves a special
mention here. Basically the memory clock is gen-
erated on-chip through a PLL and goes directly to
the MCLKO output pin of the STPC. The nominal
frequency is 100MHz. Because of the high load
presented to the MCLK on the board by the
DIMMs it is recommeded to rebuffer the MCLKO
signal on the board and balance the skew to the
clock ports of the different DIMMs and the MCLKI
input pin of STPC.
and ground planes to provide a low impedance
path between the planes for the return paths for
signal routings which change layers. If possible
the traces should be routed adjacent to the same
power or ground plane for the length of the trace.
For the SDRAM interface the most critical signal is
the clock. Any skew between the clocks at the
SDRAM components and the memory controller
will impact the timing budget. In order to get well
matched clocks at all the components it is recom-
mended that all the DIMM clock pins, STPC mem-
ory clock input (MCLKI) and any other component
using the memory clock are individually driven
BOARD LAYOUT
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