MSAN-107 Zarlink Semiconductor, Inc., MSAN-107 Datasheet - Page 14

• Manufacturer Part Number: MSAN-107
• Description: Understanding and Eliminating Latch-Up in CMOS Applications
• Manufacturer: Zarlink Semiconductor, Inc.

MSAN-107
potential
developing. Consider, for example, the case of an
analog comparator powered from
digital device powered from a +10V supply. When
the comparator output goes low, it will approach -10V
and pull the digital input below V
comparator can pull enough current, then latch-up
may be triggered. Putting a resistor in series with
the input will limit the current and prevent latch-up.
However, it is not a recommended procedure to use
the input diodes as clamping circuits.
advisable solution is to use a resistive divider as
shown in Fig. 22. When the comparator output goes
low, the divider will have 20V across it. Half of this
voltage will be dropped across each resistor so that
the digital input sits at 0V. When the comparator
output goes high, no current flows through the
divider so that the digital input sits at V
CMOS input has an extremely high input impedance,
the value of these resistors can be very large
(>100K) to minimize power consumption.
Conclusion
In the vast majority of circuits and systems
employing CMOS devices, latch-up will not be a
major concern. When simply applied according to
manufacturers‘ recommendations, CMOS devices
are not overly sensitive to the normal circuit
conditions that exist within a system. What has been
attempted in this application note is to develop an
understanding of the latch-up phenomenon and its
causes to assist designers in avoiding potential
pitfalls caused by a simple lack of knowledge.
Having briefly reviewed the basic theory of SCR
operation in general, and as it applies to CMOS input
and output structures, an understanding of the
mechanism of latch-up was developed.
close look at various aspects of system and circuit
design has revealed that various precautionary
measures taken at the design stage can greatly
A-44
Fig. 22 - Voltage Divider to Limit Voltage Swing
hazard
on CMOS Input
of
over-voltage
SS
10V driving a
DD
(0V).
. Since the
conditions
Taking a
A more
If the
reduce the risk of latch-up occurrences. In cases
where system performance or features create
potentially
designer’s control, the implementation of simple
protection circuitry will again minimize problems.
Through the use of careful design practices,
augmented by protection circuitry when needed, the
designer
integrated circuits extensively.
reliability will no longer be a function of latch-up
related problems
Reference
1.
Appendix
The following is a derivation of equation (1) of the
main text. Fig. 2 is referenced for this purpose.
The collector and emitter currents of Q
related by:
Looking at Fig. 2, it can be seen that the load current
and the emitter currents of Q1 and Q2 are all equal.
Also the load current is equal to the sums of the two
collector currents and a leakage current from Q
collector to its base (I
The collector-emitter current gains (
expressed in terms of the collector-base current
gains (B
Substituting these into the equation above yields:
I
S.B.
L
Semiconductor Circuits”, pp. 77-84, John Wiley
and Sons, 1975.
= I
= i
= (
=
1
1- (
=
I
I
1
C
CBO
L
L
1
,B
1
1
+ i
i
1+B
=
= I
can
E
+
Dewan
2
1
B
1
2
) as:
C
1
1-
hazardous
CBO
+
+
2
1
2
i
) I
C
+ I
1
2
.
2
use
L
2
1+B
=
CBO
)
i
E
B
+ I
1
2
1
(
+ I
and
1
CBO
2
CBO2
I
1+B
i
CBO
E
CMOS
CBO
1
1-
+
1
2
) (
B
2
). Therefore:
situations
2
1
A.
1+B
B
2
1 + B
Application Note
B
2
analog
)
Straughen,
2
System and circuit
2
2
=
i
C
2
=
1+B
B
1
beyond
1
,
2
and
and Q
2
2
2
i
E
) can be
2
“Power
digital
2
the
are
2
‘s