MSAN-141 Zarlink Semiconductor, Inc., MSAN-141 Datasheet
MSAN-141
Related parts for MSAN-141
MSAN-141 Summary of contents
Page 1
... Network Interface. In order to take full advantage of the contents of this note, reference must be made to the MT8930B/31B data sheets. NT2 SWITCH R R MATRIX Figure 1 - ISDN S/T Interface MSAN-141 MT8930B/31BS/T Interface ISSUE 1 November 1992 become standardized, Zarlink T NT1 S A-201 ...
Page 2
... MSAN-141 TABLE OF CONTENTS 1.0 MT8930B/31B S/T-Interface Transceiver 2.0 Access Considerations at the S-Interface 2.1 Line Code 2.2 Frame Structure 2.2.1 Terminal Framing 2.2.2 Multiframing 2.3 State Activation Machine 2.3.1 State Machine 2.3.2 Activation Times and Timers 2.3.3 INFO Detection Algorithm 2.4 D-Channel Access 2.4.1 Priority Classes 2.4.2 Collision Detection 2.5 Clocking 2.5.1 NT Slave 2.6 Loop Configurations 2.6.1 Point-to-Point 2 ...
Page 3
... F-bit is a violation). Fa-bit: The Fa-bit is the auxiliary framing bit used to secure the frame position in the presence of an idle B- and D-channel following the F-bit. The Fa and N bits can MSAN-141 ...
Page 4
... MSAN-141 A-204 Application Note ...
Page 5
... The SNIC has provisions for the detection and generation of the multiframing pattern. This same multiframe will provide a layer 1 signalling capability using the S-bit, from NT to TE, and the Q-bit, from TE to NT. The multiframe consists of a five S-Bus frame multiframe. Upon detection of the multiframe signal, MSAN-141 ...
Page 6
... MSAN-141 the TE will replace the next Fa-bit to be transmitted with the Q-bit, while the NT will insert the S-channel into the S-bit. The multiframing structure consists of five S-Bus frames which can be identified by the binary inversion of the Fa and N-bit on the first frame of the multiframe in the frame structure, i ...
Page 7
... State INFO Sent Act. Req. Deact. Req. T2 Expiry Rcv. INFO0 Rcv. INFO1 Rcv. INFO3 Lost Sync Note change / = Not applicable T2 = Start Timer 2 MSAN-141 INFO0 NT INFO1 NT NT INFO2 NT INFO3 NT INFO4 IS1 0 - deactivated (G1 pending deactivation (G4 pending activation (G2) ...
Page 8
... MSAN-141 State F3 F4/5 INFO Sent Act. Req. F4/5 / Deact. Req Rcv. INFO0 -- -- Rcv. any signal -- F5 Rcv. INFO2 F6/8 F6/8 Rcv. INFO4 F6/8 F6/8 Lost Sync / / Table 3. TE State Machine Note change / = Not applicable BA = Bus Activity Sync = Synchronization Any signal = reception of three zeros in any 48-bit ...
Page 9
... TEs access to the single 16 kbit/s D-channel. A layer 1 priority scheme has been implemented to allocate terminal priority as well as provide contention resolution. MSAN-141 A TE gains access to the D-channel when it reaches its priority count. This is accomplished by monitoring the received D-echo channel (E-bit) transmitted from the NT and counting the number of consecutive binary ones ...
Page 10
... MSAN-141 F0i NT F0od F0i NT F0od F0i NT F0od F0i operating in adaptive timing TR is the line termination resistor = 100 100m for operating is fixed timing TR is the line termination resistor = 100 operating in adaptive timing TR is the line termination resistor = 100 Figure 9 - Extended Passive Bus Confi ...
Page 11
... V DD SNIC SNIC 10K NT NT STAR STAR F0b F0b DSTi DSTi DSTo SNIC SNIC NT NT STAR STAR F0b F0b DSTi DSTi Figure Star Configuration MSAN-141 introduced by the transmission to TE Output ST-BUS Stream to TE A-211 ...
Page 12
... MSAN-141 This implies that the NT must be capable of extracting data from different sources arriving with variable delays. For this reason, the adaptive timing circuit mentioned above, must be disabled so that the receiver will not try to track the differential delays. (The adaptive timing circuit can be disabled by setting the Timing bit (B4) of the NT C-channel Control Register to a binary 0) ...
Page 13
... Application Note Figure 13 - ST-BUS Channel Assignment MSAN-141 information to and from the the TE mode, timing is generated from an on-board analog phase-locked loop which extracts timing from the received data on the S-Bus and generates the system 4096 kHz (C4b) and frame pulse (F0b). The ...
Page 14
... MSAN-141 channels on the ST-BUS can be mapped into either half of the S-Bus frame. For this reason, a HALF signal is required to identify the source or destination of the ST-BUS channels on the S-Bus frame. Figure 3 reveals the frame mapping between the ST-BUS system interface and the S-Bus line port for both the NT and TE simultaneously under zero line length condition ...
Page 15
... Control Register 1 Not Available DSTo C-channel S-Bus Tx D-channel DSTo D-channel S-Bus Tx B1-channel DSTo B1-channel S-Bus Tx B2-channel DSTo B2-channel Table 5. SNIC Address Map MSAN-141 Read verify verify verify HDLC Status Register HDLC Interrupt Status Register HDLC Rx FIFO verify verify C-channel Status Register ...
Page 16
... MSAN-141 Since the same physical register is used to receive data from the ST-BUS and transmit this information to the S-Bus, the register can not be accessed while the information of the register is being shifted in or out of the line or system ports. Therefore, the New Data Available ...
Page 17
... This terminating resistor transmission line and is thus placed at both ends of the transmit and receive pair (refer to Figures 7 to 9). With the TE presenting a high impedance on both 20 106 Frequency (kHz) MSAN-141 S Q-Bit 0.75 0.95 1.25 is relevant to ...
Page 18
... MSAN-141 2500 Z 250 200 100 2 Figure Impedance Template (log-log scale) the Rx and Tx lines, multiple TEs can be connected without altering the characteristics impedance of the line. 5.1 Transmitter Characteristics The line driver incorporated on the SNIC is a temperature compensated, voltage limited current source having a typical I-V characteristics as shown in Figure 16 ...
Page 19
... TE mode. Therefore, the VCO frequency is always centered at the proper value. Under all conditions the TE will phase-lock to the INFO2 signal within 50 ms. An inherent advantage of Peak Detector Positive Highpass Filter Peak Detector Negative Figure 21 - Receiver Circuit MSAN-141 Nominal Pulse RPos Data Recovery Circuit RNeg A-219 ...
Page 20
... MSAN-141 the analog PLL is its capability to reject input jitter. The PLL has a second order jitter transfer function with cutoff point situated at 1kHz as shown in Figure 22. Jitter out Jitter in (dB Figure 22 - Jitter Transfer Function In the NT mode, the SNIC will produce a 192 kHz baud rate clock by dividing the 4096 kHz system clock ...
Page 21
... These diodes should have similar or better electrical characteristics than the ones stated below (typical diodes are the 1N916, 1N4149, 1N4448, 1N4449, 1N3600): MSAN-141 have a passband of at least 300 kHz to 5 MHz. ...
Page 22
... MSAN-141 Breakdown Voltage Forward Current 300 mA Reverse Recovery Time 4 ns Peak Forward Surge Current Pulse Width = Pulse Width = However, to provide extra protection when the power fault conditions may exceed that of I.430 or when the interface wiring is exposed, gaz tubes can be used on the four-wire interface side ...
Page 23
... TxFIFO will not overwrite the last byte in the FIFO and cause the byte to be lost. Conversely, if the transmit FIFO underruns, the HDLC transmitter will begin sending an abort sequence (01111111) followed by the selected interframe time fill. MSAN-141 RxFIFO Status 14 Bytes 15 Bytes Table 8. RxFIFO Status TxFIFO Status ...
Page 24
... MSAN-141 8.3 Transparent Option The Trans bit (B2) in the HDLC Control Register 1 can be set to provide transparent data transfer by disabling the protocol functions. The transmitter no longer generates the Flag, Abort and Idle sequences nor does it insert the zeros and calculate the FCS. Error ...
Page 25
... When the device has only four remaining bytes in the Tx FIFO, an interrupt is issued through the TxFL bit in the HDLC Interrupt Status Register. This is a warning indicating that more data MSAN-141 The HDLC protocol on the D- This will allow the device to Interrupt Status ...
Page 26
... MSAN-141 DSTi D DSTo D HDLC Control Reister 1 = 00XXXX0X DSTi D DSTo D HDLC Tx HDLC Control Register 1 = 10X0XX0X HDLC Not Stored Tx DSTi D DSTo D HDLC Control Register 1 = 10X1XX0X HDLC Rx DSTi D DSTo D HDLC Control Register 1 = 01XX0X0X DSTi D DSTo D HDLC HDLC Rx Tx HDLC Control Register 1 = 11X01X0X Figure 29 - Possible D-channel Connections ...
Page 27
... In a passive bus configuration, there are certain procedures that all TEs on the line should follow to avoid contention and to provide fair access among all. Some of these procedures are listed as follows: MSAN-141 - When a TE has no layer 2 frames to transmit, it shall send binary ONEs on the D-channel. In other words, the interframe time fi ...
Page 28
... MSAN-141 Notes: A-228 Application Note ...
Page 29
North America - West Coast Tel: (858) 675-3400 Fax: (858) 675-3450 Tel: +65 333 6193 Fax: +65 333 6192 Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) ...