MSAN-107 Zarlink Semiconductor, Inc., MSAN-107 Datasheet - Page 5

• Manufacturer Part Number: MSAN-107
• Description: Understanding and Eliminating Latch-Up in CMOS Applications
• Manufacturer: Zarlink Semiconductor, Inc.

Application Note
This will cause the SCR to trigger as outlined in the
previous section. The second triggering mechanism
will be apparent in very few systems.
voltage spikes on the power supply rails can induce
a “dV/dt” triggering of the SCR, also as outlined
earlier. This can potentially result in circuit damage
by transients which in themselves would not have
sufficient energy to cause damage due to localized
power dissipation.
remain latched on until the supply voltage is reduced
below its sustaining voltage or if the current is
reduced below its holding current.
Input SCR Structures
Parasitic SCR structures can also result due to the
fabrication of CMOS input protection circuitry. The
ISO-CMOS input protection circuit schematic is
shown in Fig. 6. As shown, there is a distributed
diode connected to V
The series resistor is primarily intended for static
protection, but also provides latch-up protection.
The diodes are connected together at the input node.
An SCR structure results when the V
Figure 6 - Input Protection Circuit Schematic
INPUT PIN
V
DD
Once triggered, the SCR may
DD
and another diode to V
Figure 7 - Input SCR Structure with V
V
DD
TO CIRCUITRY
ON DIE
SS
referenced
Very fast
SS
.
diode is fabricated in close proximity to an N-channel
transistor (Fig. 7) or when the V
is located close to a P-channel device. (Fig. 8).
It is important to note here the difference between
input and output SCR structures. The output SCR
was connected directly between V
hence, is more likely to be destructive once
triggered.
from the input node to one of the supply rails. Thus,
for an input to remain latched, the circuitry driving
the input must be capable of supplying the sustaining
current of the SCR.
destructive, the input driver must be capable of
supplying large amounts of current.
more
complimentary transistor, to the one forming the
SCR, is located nearby. A secondary SCR structure
results from this and it is connected across the
supply rails (Figs. 7 and 8).
Consider the V
The source and drain diffusions of the P-channel
transistor form the emitters of a lateral PNP
transistor. The substrate acts as the base and the
P-diffusion of the diode is the collector. This diode,
with the substrate, forms a vertical NPN transistor.
The two transistors are interconnected as an SCR
due to common diffusion areas. If an applied input
voltage is below V
gate-cathode junction of the SCR will become
forward biased and turn the SCR on. This latch-up
condition will continue as long as this input condition
persists or if the input circuitry can supply the
minimum
potentially more hazardous situation can develop if
an N-channel transistor is also located nearby. The
P-well of this transistor serves as a second collector
of the lateral PNP transistor. When the input voltage
goes negative, the gate of the SCR is turned on as
mentioned.
injects current into the P- well causing a second SCR
dangerous
holding
The input SCR structure is connected
However, this second collector now
DD
SS
Diode
SS
referenced diode situation first.
current.
situation
by more than V
For this latch-up to be
SS
As
MSAN-107
occurs
DD
referenced diode
mentioned,
and V
A potentially
LU
, then the
when
SS
, and
A-35
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