MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet - Page 29
![no-image](/images/no-image-200.jpg)
MCC501RX166TD0B
Manufacturer Part Number
MCC501RX166TD0B
Description
Network Processor, 16 Processing Elements, 166MHz Core Operating Frequency, 5Gbps Max Throughput, 838-CBGA
Manufacturer
Motorola / Freescale Semiconductor
Datasheet
1.MCC501RX166TD0B.pdf
(98 pages)
- Current page: 29 of 98
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Table 8 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued)
*
†
C-Port Confidential
Signal Name* Pin #† Total Type
CPn+1_6
CPn+2_0
CPn+2_1
CPn+2_2
CPn+2_3
CPn+2_4
CPn+2_5
CPn+2_6
CPn+3_0
CPn+3_1
CPn+3_2
CPn+3_3
CPn+3_4
CPn+3_5
CPn+3_6
Total Pins
n can be 0, 4, 8, or 12.
Reference
Table 4
for pin numbers for the actual cluster(s) you are configuring.
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
Table 4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
28
Gigabit Ethernet and Fibre Channel TBI Configuration
1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same
way as Gigabit Ethernet (GMII).
use and
the signals and pinouts for a single cluster for Gigabit Ethernet and Fibre Channel TBI.
LVTTL
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
I/O
O
I
I
I
I
I
I
nc
I
I
I
I
I
I
Figure 3
Label
TX_ER
nc
RCLK
RXD(0)
RXD(1)
RXD(2)
RXD(3)
RX_DV
nc
CRS
RXD(4)
RXD(5)
RXD(6)
RXD(7)
RX_ER
shows receive and transmit pin configurations by cluster.
Signal Description
Transmit Error. Asserting TX_ER when TX_EN is a 1 causes
transmission of the designated “bad code” in lieu of the normal
encoded data on the twisted pair data.
nc
Receive Clock (125MHz)
Receive Data (byte-wide receive data, least significant bit)
Receive Data
Receive Data
Receive Data
Receive Data Valid. Indicates that there is a receive frame in progress
and that the data present on the RXD signals is valid.
nc
Carrier Sense. Indicates traffic is on the link. CRS is asserted when a
non-idle condition is detected on the receive data stream. CRS is
deasserted when an end of frame or idle condition is detected.
Receive Data
Receive Data
Receive Data
Receive Data (most significant bit)
Receive Error Detected. Indicates that there has been an error
received in the receive frame.
Table 7
shows the possible CP pin combinations you can
Pin Descriptions Grouped by Function
Preliminary Version — January 21, 2002
Table 9
shows
29
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