MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet - Page 34

• Manufacturer Part Number: MCC501RX166TD0B
• Description: Network Processor, 16 Processing Elements, 166MHz Core Operating Frequency, 5Gbps Max Throughput, 838-CBGA
• Manufacturer: Motorola / Freescale Semiconductor

34
Table 12 PCI Signals (continued)
January 21, 2002— Preliminary Version
Signal Name
PTRDYX
PIRDYX
PSTOPX
PDEVSELX
PPERRX
PSERRX
PCLK
PRSTX
PREQX
PGNTX
PIDSEL
PINTA
Total Pins
C
HAPTER
2: S
IGNAL
Pin #
L20
L19
K18
N18
M18
L18
L15
N17
L17
N19
O18
O16
D
ESCRIPTIONS
Serial Interface Signals
The Serial interface is a bidirectional two-wire serial bus. It can use one of the following
formats:
1 An 8bit data format followed by an acknowledge bit, which supports transfers at up to
2 a 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports
The signals and pins are identical for both the high and low speed protocols.
Which of the two data rates used is selected by the state of the PROM interface’s SPLD
signal that is asserted while the PROM interface is idle. When SPLD is asserted HI the low
speed serial bus protocol is selected and when SPLD is asserted LOW the MDIO protocol is
selected.
The bus only supports a single master hierarchy that can operate as either a receiver or a
transmitter. The bus also supports collision detection and arbitration, and an integrated
addressing and data-transfer protocol.
Both SIDA and SICL are bidirectional lines that are connected, through a pull-up resistor,
to a positive supply voltage. When the bus is free, both lines are HIGH. The output stages
400kbps (low speed).
transfers up to 25MHz (high speed).
Total Type
1
1
1
1
1
1
1
1
1
1
1
1
50
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
O
I
I
O
Signal Description
Target ready for data transfer
Initiator ready for data transfer
Target transaction stop request
Target device selected
Bus parity error
System error
Bus clock
Bus reset
Initiator bus request (arbitration)
Initiator bus grant (arbitration)
Initialization device select
Interrupt
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