MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet - Page 44

• Manufacturer Part Number: MCC501RX166TD0B
• Description: Network Processor, 16 Processing Elements, 166MHz Core Operating Frequency, 5Gbps Max Throughput, 838-CBGA
• Manufacturer: Motorola / Freescale Semiconductor

44
Table 22 TLU SRAM Interface Signals
January 21, 2002— Preliminary Version
Signal Name
TD0 - TD63
TA0 - TA21
TA18x - TA21x
TCE0X - TCE3X
TWE0X - TWE3X
TCLKI
Total Pins
TLU SRAM Interface
C
HAPTER
2: S
IGNAL
Pin #
N1, L1, J1, H1, M2, K2, I2, G2, N2, L2, J2, H2, L3, J3,
H3, G4, 04, M4, K4, I4, L4, J4, H4, G6, N5, L5, J5, H5,
N6, L6, I6, H6, K6, J6, M6, H7, L7, J7, H8, N8, M8, K8,
I8, G8, N7, L8, J8, H9, L9, J9, J10, G10, P9, O8, L10,
H10, O10, N9, L11, I10, M10, K10, J11, H11
R1, P1, S2, Q2, O2, R2, P2, R3, P3, N3, S4, Q4, R4, P4,
N4, R5, P5, S6, R6, Q6, P6, O6
T8, Q8, R7, P7
P8, R8, S8, T9
Q10, R9, S10, T10
M12
Signals
D
ESCRIPTIONS
The TLU SRAM interface supports up to 32MBytes of SRAM at frequencies to 133MHz
using LVTTL signaling levels (in single bank-mode only) and SRAM technologies up to
64Mbits. The TLU SRAM interface signals are described in
Table 23 Memory Bank Selection
Size
4Mbit
8Mbit
16Mbit
CE2
TA18x
TA19x
TA20x
Bank 1
CE2x
TA19
TA20
TA21
CE2
TA18
TA19
TA20
Chip Select (Signals TA18x through TA21x)
Total
64
22
4
4
4
1
99
Bank 2
CE2x
TA19
TA20
TA21
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
I/O
I/O
O
O
O
O
I
CE2
TA18x
TA19x
TA20x
Signal Description
TLU Memory Data
TLU Memory Address
Data Parity
TLU Memory Chip Enable
TLU Memory Write Enable
TLU Clock Input
Bank 3
Table 22
CE2x
TA19x
TA20x
TA21x
.
CE2
TA18
TA19
TA20
C-Port Confidential
Bank 4
CE2x
TA19x
TA20x
TA21x