MCC501RX166TD0B Motorola / Freescale Semiconductor, MCC501RX166TD0B Datasheet - Page 66

• Manufacturer Part Number: MCC501RX166TD0B
• Description: Network Processor, 16 Processing Elements, 166MHz Core Operating Frequency, 5Gbps Max Throughput, 838-CBGA
• Manufacturer: Motorola / Freescale Semiconductor

66
January 21, 2002 — Preliminary Version
Power Sequencing
C
HAPTER
3: E
LECTRICAL
S
PECIFICATIONS
The VDD rail must be kept within 2.5V of the VDD33 rail. However, this rule can be violated
for periods up to one second, as is typical during power sequencing, as long as:
•
•
It is intended that the VDD and VDD33 rail be sequenced to their final value together for
most applications.
It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running
or begin running during power sequencing to propagate reset inside the C-5 NP.
indicates the relationship between the clocks and PRSTX. There is no requirement that the
asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be
asserted within 100 s of power initiation. Typically, reset is held low during power
initiation.
Figure 9 Bringup Clock Timing Diagram
MDCLK, FTXCLK,
SCLK, SCLKX,
The VDD is not clamped to ground or some other low voltage.
The number of power cycling events averages to less than once per day over the
lifetime of the product.
TCLKI, PCLK,
VDD, VDD33
FRXCLK
PRSTX
100 s
³
1ms
)
)
³
100 s
(
(
C-Port Confidential
Figure 9