A43P26161 AMIC Technology, Corp., A43P26161 Datasheet
A43P26161
Related parts for A43P26161
A43P26161 Summary of contents
Page 1
... X 16 Bit X 4 Banks Low Power Synchronous DRAM Revision History Rev. No. History 0.0 Initial issue 1.0 Modify to 133MHz & 105MHz Modify all DC specification for new product 1.1 Modify t from 3ns to 2ns SS PRELIMINARY (July, 2005, Version 1.1) A43P26161 Issue Date Remark September 13, 2004 Preliminary June 10, 2005 July 11, 2005 AMIC Technology, Corp. ...
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... VSSQ VDDQ 15 DQ VDDQ VSSQ 13 DQ VSSQ VDDQ 11 DQ VDDQ VSSQ 9 NC VSS VDD 8 CLK CKE CAS A11 A9 BA0 A43P26161 high performance memory VDD LDQM DQ 7 RAS WE BA1 CS A1 A10 A2 VDD AMIC Technology, Corp ...
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... Data Input Register Column Decoder Latency & Burst Length Programming Register LCAS LWE Timing Register CKE CS RAS CAS WE 2 A43P26161 29 LWE DQM DQi DQM LWCBR DQM AMIC Technology, Corp. 28 ...
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... Enables write operation and Row precharge. Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power Supply: +2.3V ~ 2.7V/Ground Provide isolated Power/Ground to DQs for improved noise immunity. 3 A43P26161 AMIC Technology, Corp. ...
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... VDDQ - 0 -1.5 OL See Fig. 1 (Page 6) 4 Min 2.0 CAS DQM 2.0 3.5 =-40ºC to +85ºC for extended) A Max Unit 2 VDDQ+0 0 0.2 V µ µ 1.5 AMIC Technology, Corp. A43P26161 Max Unit 4.0 pF 4.0 pF 6.0 pF Note Note -0.1mA 0.1mA OL Note 2 Note 3 ...
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... Input signals are changed one time during 30ns I = 0mA, Page Burst OL All bank Activated (min) CCD CCD ≥ (min TCSR Range CKE ≤ 0.2V CKE ≤ 0.2V 5 A43P26161 Value Unit µ F 0.1 + 0.01 µ F 0.1 + 0.01 = -40ºC to +85ºC for extended) A Speed -75 -95 40 0.3 0.5 5.5 = ∞ ...
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... VDDQ-0.2V -0.1mA OH OH 500Ω V (DC) = 0.2V 0.1mA OL OL 30pF -75 Min CL=3 7.5 CL=2 12 CL=3 - CL=2 - 2.5 CL=3 3 CL=2 3 CL=3 3 CL=2 3 CL=3 2 CL=2 2 1.5 1 CL A43P26161 Value V =0.5V x VDDQ TT 50Ω Z =50Ω OUTPUT O 30pF (Fig Output Load Circuit -95 Max Min Max 9.5 1000 1000 3.5 - ...
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... CCD(min) Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. PRELIMINARY (July, 2005, Version 1.1) Parameter 7 A43P26161 Version Unit -75 - CLK ...
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... Valid Don’t Care Logic High Logic Low) 8 A43P26161 WE DQM BS0 A10 A9~A0, BS1 /AP A11 CODE CODE Row Addr. L Column Addr ...
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... Banks to be Self-Refreshed Bank A, Bank 1/2 of Bank 1/4 of Bank AMIC Technology, Corp. A43P26161 A1 A0 Burst Length BT Reserved Reserved Reserved Reserved Address Bus (Ax) All banks Bank A Reserved Reserved Reserved ...
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... A43P26161 Interleave Interleave ...
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... A. The TCR field has four entries to set Refresh Period during self-refresh depending on the case temperature of the Low Power devices. The Extended Mode Register is programmed via the Mode Register Set command (with BS0=0 and BS1=1) and retains 11 A43P26161 WE CAS , and BS1 ...
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... A10/AP. If burst read or burst write command is issued with low on A10/AP, the bank is left active until a new command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state. 12 A43P26161 CS , CAS ” after the last data input to be RDL ...
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... Power SDRAMs with very low standby currents. All internal voltage generators inside the Low Power SDRAMs are stopped and all memory data will be lost in this mode. To enter the Deep Power Down Mode all banks must be precharged and the necessary Precharged Delay t occur. 13 A43P26161 CS , RAS , and CKE with high on CAS ” ...
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... DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”. 2. DQM masks both data-in and data-out. PRELIMINARY (July, 2005, Version 1.1) 2) Clock Suspended During Read (BL= Read Mask (BL= Hi-Z Hi Hi-Z Hi A43P26161 Masked by CKE Suspended Dout Masked by CKE Hi Hi DQM to Data-out Mask = 2 Hi-Z Q6 ...
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... Last data in to new column address delay. (= 1CLK). CDL PRELIMINARY (July, 2005, Version 1.1) Note 1 QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 DQ(CL2) DQ(CL3) access; read, write and block write. CAS 15 A43P26161 3) Write interrupted by Read (BL = CCD Note2 A B DA0 QB0 QB1 DA0 QB0 t CDL Note3 AMIC Technology, Corp ...
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... To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out. PRELIMINARY (July, 2005, Version Note Hi Hi Note 2 16 A43P26161 AMIC Technology, Corp. ...
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... Version 1.1) Note 2 PRE Note 1 D3 PRE RDL PRE Note 1 Auto Precharge Starts Note 1 Auto Precharge Starts interrupt of the same/another bank is illegal. CAS 17 A43P26161 from this point. RP AMIC Technology, Corp. ...
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... Version 1.1) 2) Write Burst Stop (BL=8) CLK CMD PRE DQM Note 1 RDL 4) Read Burst Stop (BL=4) CLK CMD Note DQ(CL2 DQ(CL3) MRS ACT t 2CLK RP 18 A43P26161 WR STOP Note 2 BDL RD STOP AMIC Technology, Corp. ...
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... Before/After self refresh mode, burst auto refresh cycle (4K cycles ) is recommended. PRELIMINARY (July, 2005, Version 1.1) 2) Power Down (=Precharge Power Down) Exit t SS Internal CLK A43P26161 CLK CKE t SS Note 2 NOP ACT CMD Note 5 CMD CMD t RC AMIC Technology, Corp. ...
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... During read/write burst with auto precharge, RAS interrupt cannot be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. During read/write burst with auto precharge, 20 A43P26161 interrupt can not be issued. CAS AMIC Technology, Corp. ...
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... DQM High level is necessary High Precharge Auto Refresh (All Banks) PRELIMINARY (July, 2005, Version 1. Auto Refresh 21 A43P26161 KEY KEY t RC Normal Extended MRS MRS : Don't care AMIC Technology, Corp Row Active ...
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... *Note 2,3 *Note 2 *Note 3 *Note SLZ SHZ Write Read 22 A43P26161 *Note 4 *Note *Note Row Active Precharge AMIC Technology, Corp Don't care ...
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... Enable auto precharge, precharge bank B at end of burst Enable auto precharge, precharge bank C at end of burst Enable auto precharge, precharge bank D at end of burst. BS1 BS0 Precharge 0 0 Bank Bank Bank Bank All Banks 23 A43P26161 Operation AMIC Technology, Corp. ...
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... SHZ t OH Qa0 Qa1 Qa2 Qa3 *Note SHZ SAC Precharge Row Active (A-Bank) (A-Bank) from the clock. SHZ *(t + CAS latency- RCD 24 A43P26161 Cb0 Rb Db0 Db1 Db2 Db3 t RDL Db0 Db1 Db2 Db3 t RDL Write (A-Bank) SAC AMIC Technology, Corp ...
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... High Cb *Note1 Qb2 Qa0 Qa1 Qb0 Qb1 Qa0 Qa1 Qb0 Qb1 Read (A-Bank) before Row precharge, will be written. RDL 25 A43P26161 *Note RDL t CDL *Note3 Dc0 Dc1 Dd0 Dd1 Dc0 Dc1 Dd0 Dd1 Write ...
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... Precharge Precharge Row Active (A-Bank) (B-Bank) (C-Bank) WE CAS RAS , and are high at the clock high going edge. 26 A43P26161 *Note 2 CDd QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2 Read Precharge (D-Bank) ...
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... High CBb RCc RDd RCc RDd DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 t CDL Write Row Active (B-Bank) (D-Bank) Row Active (C-Bank) 27 A43P26161 CCc CDd DCc0 DCc1 DDd0 DDd1 CDd2 t RDL *Note 1 Precharge Write (All Banks) (D-Bank) Write (C-Bank) AMIC Technology, Corp ...
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... Row Active (D-Bank CDb RBc CBc RBC t CDL *Note 1 DDb0 DDb1 DDb2 DDb3 DDb0 DDb1 DDb2 DDb3 Write Read (D-Bank) (B-Bank) Row Active (B-Bank) AMIC Technology, Corp. A43P26161 18 19 QBc0 QBc1 QBc2 QBc0 QBc1 : Don't care ...
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... QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 QAa3 Auto Precharge Read with Start Point (A-Bank/CL=3) (A-Bank) Auto Precharge Start Point (A-Bank/CL=2) 29 A43P26161 CBb DDb0 DDb1 DDb2 DDb3 DDb0 DDb1 DDb2 DDb3 Write with Auto Precharge (D-Bank) AMIC Technology, Corp. ...
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... PRELIMINARY (July, 2005, Version 1. Qa0 Qa1 Qa2 Qa3 t SHZ Read Clock Bank 0 Suspension Note 1 Qb0 Qb1 Dc0 Dc2 t SHZ Write DQM Read DQM Write Clock Bank 0 Suspension AMIC Technology, Corp. A43P26161 Don't care ...
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... High CAb 1 QAa0 QAa1 QAa2 QAa3 QAa4 2 QAa0 QAa1 QAa2 QAa3 QAa4 Read Burst Stop (A-Bank) 31 A43P26161 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 QAb0 QAb1 QAb2 QAb3 Precharge (A-Bank) RAS interrupt. AMIC Technology, Corp QAb4 QAb5 ...
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... PRELIMINARY (July, 2005, Version 1. High CAb t BDL DAa1 DAa2 DAa3 DAa4 DAb0 Write Burst Stop (A-Bank) (=2CLK). RDL RDL * Note 2 DAb1 DAb2 DAb3 DAb4 DAb5 Precharge AMIC Technology, Corp. A43P26161 18 19 (A-Bank) : Don't care ...
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... Note Precharge Power-down Exit Row Active Active Active Power-down Power-down Exit Entry ” prior to Row active command A43P26161 SHZ Qa0 Qa1 Qa2 Read Precharge : Don't care AMIC Technology, Corp ...
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... If the system uses burst refresh. PRELIMINARY (July, 2005, Version 1. Note 4 * Note 3 Hi-Z Self Refresh Exit 34 A43P26161 min Note 6 * Note 5 * Note 7 Auto Refresh AMIC Technology, Corp ...
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... Please refer to Mode Register Set table. PRELIMINARY (July, 2005, Version 1.1) Auto Refresh Cycle Auto Refresh WE activation at the same clock cycle with address key will set internal RAS activation. 35 A43P26161 High t RC Hi-Z AMIC Technology, Corp New Command ...
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... Deep Power Down Mode Entry CLK CKE CS WE CAS RAS ADDR DQM DQ input DQ output PRELIMINARY (July, 2005, Version 1.1) High Precharge Command Deep Power Down Entry Normal Mode Deep Power Down Mode 36 A43P26161 AMIC Technology, Corp. ...
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... Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extended mode register PRELIMINARY (July, 2005, Version 1. All Banks Auto Precharge Refresh Refresh Mode Extended Auto Register Mode Set Register Set AMIC Technology, Corp. A43P26161 New Command Accepted Here ...
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... NOP(Continue Burst to End → Precharge NOP(Continue Burst to End → Precharge ILLEGAL H BS CA,A10/AP ILLEGAL L BS CA,A10/AP ILLEGAL X BS RA, PA ILLEGAL ILLEGAL 38 A43P26161 Action Note AMIC Technology, Corp. ...
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... NOP → Idle after 2 clocks NOP → Idle after 2 clocks ILLEGAL ILLEGAL ILLEGAL BS = Bank Address CA = Column Address 39 A43P26161 Action RCD RCD Auto Precharge PA = Precharge All AMIC Technology, Corp. Note ...
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... X X Refer to Operations in Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain clock Suspend 40 A43P26161 Action RC RC (min) has to be elapse before issuing a RC AMIC Technology, Corp. Note ...
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... A43P26161G-75U 7.5 A43P26161G-75UF 7.5 A43P26161V-75 7.5 A43P26161V-75F 7.5 A43P26161V-75U 7.5 A43P26161V-75UF 7.5 A43P26161G-95 9.5 A43P26161G-95F 9.5 A43P26161G-95U 9.5 A43P26161G-95UF 9.5 A43P26161V-95 9.5 A43P26161V-95F 9.5 A43P26161V-95U 9.5 A43P26161V-95UF 9.5 Note for industrial operating temperature range -40ºC to +85ºC. PRELIMINARY (July, 2005, Version 1.1) Max. Clock Frequency Access Time (MHz) 133 133 133 133 133 133 133 ...
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... Ball ( mm) Outline Dimensions PRELIMINARY (July, 2005, Version 1. E/2 Max. 0.20 b Encapsulant Dimensions in mm Symbol MIN. NOM 0.20 0. 7.95 8.00 E 6.40 BSC 1 D 7.95 8.00 D 6.40 BSC 1 e 0.80 BSC b 0.30 0. A43P26161 unit MAX. 1.00 0.30 8.05 8.05 0.40 0.10 AMIC Technology, Corp. ...
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... REF 1 R 0.005 - - 1 R 0.005 - 0.010 2 θ 0° - 8° 43 unit: inches/mm Detail "A" θ Detail "A" Dimensions in mm Min Nom Max - - 1.20 0.05 - 0.15 0.95 1.00 1.05 0.30 - 0.45 0.12 - 0.21 22.22 BSC 0.71 REF 11.76 BSC 10.16 BSC 0.80 BSC 0.40 0.50 0.60 0.80 REF 0. 0.12 - 0.25 0° - 8° AMIC Technology, Corp. A43P26161 0.21 REF 0.665 REF ...