A43P26161 AMIC Technology, Corp., A43P26161 Datasheet - Page 27

• Manufacturer Part Number: A43P26161
• Description: 1M x 16-Bit x 4 Banks Low Power Synchronous DRAM
• Manufacturer: AMIC Technology, Corp.

Page Read Cycle at Different Bank @Burst Length = 4
PRELIMINARY
CLOCK
A10/AP
ADDR
(CL=2)
(CL=3)
CKE
RAS
CAS
BS0
DQM
DQ
DQ
BS1
CS
WE
* Note : 1.
*Note 1
0
Row Active
(A-Bank)
RAa
RAa
2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
1
(July, 2005, Version 1.1)
CS
2
Row Active
can be don’t care when
(B-Bank)
RBb
RBb
3
(A-Bank)
Read
CAa
4
5
Row Active
(C-Bank)
QAa0 QAa1 QAa2
RCc
RCc
6
RAS
(B-Bank)
Read
QAa0 QAa1 QAa2
CBb
7
,
Precharge
CAS
(A-Bank)
8
Row Active
(D-Bank)
and
QBb0
RDd
RDd
9
26
WE
(C-Bank)
High
Read
QBb1
QBb0
CCc
10
are high at the clock high going edge.
Precharge
(B-Bank)
QBb2
QBb1
11
QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
QBb2
12
(D-Bank)
QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
Read
CDd
13
Precharge
(C-Bank)
14
AMIC Technology, Corp.
15
Precharge
(D-Bank)
16
*Note 2
17
A43P26161
: Don't care
18
19