PM8621 PMC-Sierra, Inc., PM8621 Datasheet - Page 114

• Manufacturer Part Number: PM8621
• Description: NSE-8G Standard Product Data Sheet Preliminary
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
Register 112h + N*20H, ILC Transmit Misc.Status and FIFO Synch Register
This register serves a dual purpose dependant on whether it is being read or written.
When it is read it returns the status for the Message Transmit Channel.
When it is written (with 0001h) to it is used it synchronize the Transmit FIFO to the start of a
message boundary.
TX_XFER_SYNC
TX_FI_BUSY
Bit
Bit 31:16
Bit 15
Bit 14:13
Bit 12:11
Bit 10:8
Bit 7:6
Bit 5:2
Bit 1
Bit 0
Writing ‘1’ to this bit initializes the next write sequence to be to the beginning of the next
message. After a ‘1’ had been written successive writes to the Transmit FIFO will be to
location zero of the next available slot. If a partial message has been written,
TX_XFER_SYNC indicates that the current message is complete and that subsequent writes
will be to the next message. If more than 32 bytes are written, the 33rd byte will be the first
byte of the next message. The purpose of this bit is to unambiguously align the message
boundaries. Another use would be to abandon the current write and move the write pointer to
the beginning of the next message. (Previous message data will remain in the unwritten
portion of the message being abandoned, which will have to be ignored by the receiving
software).
If the message FIFO pointers are already at a message boundary then writing this bit to a ‘1’
will have no affect.
On reads this bit is always returned as a ‘0’.
This bit indicates that the internal hardware is transferring the data from the Transmit FIFO
registers (TDAT) into the internal RAM. This bit need not be read by software if the time
interval between successive 32 bit transfers is greater than 3 SYSCLK cycles.
User and Page bits are a copy of the User bits received, and being transmitted in 0Ch. These
allow one read in the 32 bit device to gain a snapshot of the entire ILC.
Type
R
R
R
R
R
R
R
W
TX_MSG_LVL_VALID
IPAGE[1:0]
IUSER[2:0]
TX_FI_BUSY
TX_XFER_SYNC
Function
Unused
TX_LINK[1:0]
Reserved
TX_MSG_LVL[3:0]
NSE-8G™ Standard Product Data Sheet
Default
X
N/A
00
N/A
N/A
00
0000
0
0
Preliminary
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