PM8621 PMC-Sierra, Inc., PM8621 Datasheet - Page 144

• Manufacturer Part Number: PM8621
• Description: NSE-8G Standard Product Data Sheet Preliminary
• Manufacturer: PMC-Sierra, Inc.

12.5 Controlling Frame Alignment in the Receive Port
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-2010850, Issue 1
After external data corruption on any port it may be necessary to force OCA to reset the
alignment of the R8TD block. In order to detect this out of alignment condition, three hardware
functions are implemented for each port. The registers are:
These are qualified against a delayed version of the RC1FP input, which should occur every 4 or
48 frames and in agreement with mf_swap mode (DCB Configuration Register, 04Ch). If all
active ports are using carrying the same frequency of C1 frame pulses (1 in 4 or 1 in 48) then the
unexpected interrupt (013h) should be used to signal that a C1 code word was detected at the
wrong time, software can then poll the monitor register (012h) to see if the error condition is
permanent.
NSE Frame
Interrupt
NSE CPU
RC1FP (ext)
NSE C1FP
Enable Frame
tasks
“Correct R8TD_RX_C1 Pulse Monitor”, 012h
“Unexpected R8TD_RX_C1 Pulse Interrupt”, 013h
“Missing R8TD_RX_C1 Pulse Interrupt”, 014h
DCB sample
SBS sample
Interrupt
(int)
new bit
new bit
Write new SBS
page words
1
bit and set up page switch
NSE DCB samples CMP
messages
outgoing
Write new DCB
disable Frame
2
page bit and
interrupt
3
4
SBS samples new page
bits and set up page
switch
NSE-8G™ Standard Product Data Sheet
1
messages
outgoing
Switch occurs in the NSE
2
Switch occurs in the SBS
3
4
Preliminary
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