STE10-100A STMicroelectronics, STE10-100A Datasheet - Page 69
STE10-100A
Manufacturer Part Number
STE10-100A
Description
Pci 10/100 Ethernet Controller With Integrated Phy
Manufacturer
STMicroelectronics
Datasheet
1.STE10-100A.pdf
(82 pages)
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STE10/100A
Table 14.
TDES2
TDES3
21-11
28,27
31~0
31~0
10-0
Bit#
29
26
25
24
23
22
Transmit descriptor description (continued)
Name
TBS2
TBS1
TCH
DPD
TER
BA1
BA2
AC
FS
---
---
First descriptor
Reserved
Disable add CRC function
End of ring
2nd address chain. Indicates that the buffer 2 address is the next descriptor
address
Disable padding function
Reserved
Buffer 2 size
Buffer 1 size
Buffer address 1. No alignment limitations imposed on the transmission
buffer address.
Buffer address 2. No alignment limitations imposed on the transmission
buffer address.
Description
Registers and descriptors description
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