STE10-100A STMicroelectronics, STE10-100A Datasheet - Page 77
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STE10-100A
Manufacturer Part Number
STE10-100A
Description
Pci 10/100 Ethernet Controller With Integrated Phy
Manufacturer
STMicroelectronics
Datasheet
1.STE10-100A.pdf
(82 pages)
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STE10/100A
Figure 20. Serial EEPROM timings
Table 25.
Figure 21. Normal link pulse timings
Table 26.
Symbol
Symbol
Tflcpp
Tflcpd
Tnpw
Tflpw
Tflbw
Tnpc
Tflbp
-
NLP width
NLP period
FLP Width
Clock pulse to clock pulse
period
Clock pulse to data pulse
period
Number of pulses in one
burst
Burst width
FLP burst period
10BASE-T normal link pulse (NLP) timings specifications
Auto-negotiation fast link pulse (FLP) timings specifications
CLK
CS
DI
Parameter
Parameter
Tnpw
Tecss
Tedts
10Mbps
10Mbps
Tedth
Test condition
Test condition
Tnpc
Electrical specifications and timings
Tecsh
Min.
Min.
55.5
Tecsl
111
17
8
8
Typ.
Typ.
62.5
100
100
125
16
2
Max.
Max.
69.5
139
24
33
24
Units
Units
77/82
ms
ms
ms
ns
ns
µs
µs
#
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