S1D12200 Epson Electronics America, Inc., S1D12200 Datasheet - Page 71

• Manufacturer Part Number: S1D12200
• Description: S1d12000 Series Lcd Driver Ic Technical Manual Technical Manual
• Manufacturer: Epson Electronics America, Inc.

6. FUNCTION DESCRIPTION
MPU Interfaces
Interface type selection
Table 1
The S1D12205 Series has the C86 pin for MPU selection.
If the parallel input is selected (PS=HIGH), if can be
connected directly to the 80-series or 68-series MPU by
Table 2
Interface to 4-bit MPU
If the 4-bit interface is selected (IF=LOW), the 8-bit
command and data, and its address are transferred in two
times.
Note: During continuous writing, the write time greater than the system cycle time (tcyc) must be set before the
Serial interface
The serial interface consists of an 8-bit shift register and
a 3-bit counter. During chip select (CS=LOW), an SI
input and an SCL input can be accepted. During no chip
select (CS=HIGH), the shift register and counter is
initialized (reset).
Serial data of D7 to D0 are fetched in this order from the
serial data input pin (SI) at the rising edge of serial clock.
The data is converted into 8-bit parallel data at the rising
edge of the eighth serial clock.
The serial data input (SI) is identified to have the display
data or command by the A0 input. It is display data if
Rev. 1.1
HIGH Parallel input
LOW
C86 pin signal
PS
HIGH
LOW
subsequent write operation.
Serial input
Type
D7 to D4
WR
CS
80 series
68 series
Type
CS
CS
CS
A0
A0
A0
A0
A0
A0
HIGH, LOW
WR
WR
E
WR
WR
Upper (D7 to D4)
CS
CS
CS
EPSON
D0 to D7
D0 to D7
D0 to D7
SI
SI
–
The S1D12205 Series can transfer data via the 4- or 8-bit
data bus or via the serial data input (SI). The parallel or
serial data input can be selected by setting the PS pin to
HIGH or LOW (see Table 1).
setting the C86 pin to HIGH or LOW (see Table 2). Also,
the 8-bit or 4-bit data bus can be selected by the IF pin
signal.
A0=HIGH, and it is command if A0=LOW.
The A0 input is fetched and identified at the rising edge
of “8 n-th” serial clock (SCL). Figure 1 shows a serial
interface timing chart.
The SCL signals must be well protected from the far-end
reflection and ambient noise due to increased line length.
The operation checkout on the actual machine is
recommended.
Also, we recommend to repeat periodical command
writing and status refreshing to avoid a malfunction due
to noise.
SCL
SCL
–
D0 to D7
D0 to D7
Lower (D3 to D0)
–
S1D12205 Series
3–9