S1D12200 Epson Electronics America, Inc., S1D12200 Datasheet - Page 72

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S1D12200

Manufacturer Part Number
S1D12200
Description
S1d12000 Series Lcd Driver Ic Technical Manual Technical Manual
Manufacturer
Epson Electronics America, Inc.
Datasheet
S1D12205 Series
Data bus signal identification
The S1D12205 Series identifies the data bus based on a
combination of A0, WR and E signals as defined on
Table 3.
Table 3
Chip Select
The S1D12205 Series has an Chip Select pin (CS) to
allow an MPU interface input only if CS=LOW.
During no chip select status, all of D0 to D7, A0, WR, SI
and SCL inputs are made invalid. If the serial input
interface is selected, the shift register and counter are
reset.
However, the Reset signal is entered independent from
the CS status.
Power Circuit
The built-in power circuit featuring the low power
Common 68 Series 80 Series
3–10
A0
1
0
SCL
CS
A0
SI
E
1
1
V
V
DD
SS
= 0V
WR
0
0
1
D7
Writes to the RAM and symbol register.
Writes to the internal (commands) register.
2
D6
V
REG2
V
Voltage
drop
5
3
= 4 x V
D5
Voltage boost
EPSON
Figure 1
REG2
4
D4
Function
consumption generates the required LCD drive voltages.
The power circuit consists of an booster and a voltage
regulator.
Booster Circuit
When the capacitors are connected to the OCA, OCB,
OCC, OCD, OCE, V
are generated.
As the booster uses the signals from the oscillator, the
oscillator or an external clock must be operating.
The following provides the potential relationship.
5
D3
6
D2
LCD drive voltages
V
V
V
V
V
0
1
2
4
5
, V
REG2
= V
7
3
D1
DD
pins, the LCD drive voltages
8
D0
A0
1
D7
Rev. 1.1

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