S1D13503 Epson Electronics America, Inc., S1D13503 Datasheet - Page 110

• Manufacturer Part Number: S1D13503
• Description: S1d13503 Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 14
S1D13503
X18A-G-002-06
AUX[00h] 0000 0000 •
AUX[01h] 0100 0101
AUX[02h] 0100 1111
AUX[03h] 0000 0000
AUX[04h] 1110 1111
AUX[05h] 0000 0000
Register
AUX
Note
The S5U13503B00C evaluation board maps the 128K of display memory into two banks of 64K, start-
ing at D000:0000. This permits a VGA card to work along with the S1D13503B00C card. Bank 0 repre-
sents the first 64K of display memory, and is selected by reading from the base port address+2. Bank 1
represents the second 64K of display memory, and is selected by writing to the base port address+2. The
values read from or written to the base port address+2 are not important; only the action of reading or
writing is significant. This method of memory banking will only work if the S5U13503B00C is set for
indexed port I/O and is specific to this board.
Example 2:
Program S1D13503 Registers in the following order with the data supplied:
(in Binary)
Data
Initialize the registers for a 4 gray shade 640 x 480 dual panel LCD with 128k of display
memory. Afterwards write one pixel to the top left corner of the display’s second panel.
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procedure is to turn this bit off during register initialization and
afterwards turn this bit on)
supply design (for S5U13503B00C, set bit to 0 to disable power
supply) (application specific; the recommended procedure is to
disable the power supply during register initialization and
afterwards enable the power supply)
(application specific)
operation set to 00b)
(implementation and panel specific)
(panel specific)
see AUX[04h])
bits 7 and 6 must be zero
b7 = display off (application specific; the recommended
b6 = dual panel (panel specific)
b5 = XSCL not masked (panel specific)
b4 = LCDE = LCDENB pin = set to disable specific power
b3 = 4 grays when combined with AUX[03] bits 1 and 2
b2 = 8 bit LCD data width (panel specific)
b1 = 16 bit Memory Interface (implementation specific)
b0 = RAMS ignored (implementation specific)
bits 7-0 = bits 7-0 of Line Byte Count
bit 8 of Line Byte Count is bit 0 of AUX[03h]
bits 7-6 = Power Save Mode 0 (application specific - for normal
bit 5 = LCD interface signals forced low during Power Save
bit 4 = no LUT bypass (application specific)
bit 3 = 4 bit LCD data width when combined with AUX[01] bit 2
bit 2 = 4/16 gray shade mode (application specific)
bit 1 = monochrome panel attached (panel specific)
bit 0 = bit 8 of Line Byte Count (panel specific, see AUX[02h])
bits 7-0 = bits 7-0 of Total Display Line Count
bits 9-8 of Total Display Line Count in bits 1-0 of AUX[05h]
bits 7-2: 0 = WF output toggles every frame (panel specific)
bits 1-0 = bits 9-8 of Total Display Line Count (panel specific,
Notes
Epson Research and Development
Programming Notes and Examples
Vancouver Design Center
see Note A at end of
Table for calculation
see Section 5.6, “Power
Saving” on page 54
see Note B and C at end
of Table for calculation
Issue Date: 01/01/30
See Also