S1D13503 Epson Electronics America, Inc., S1D13503 Datasheet - Page 130

• Manufacturer Part Number: S1D13503
• Description: S1d13503 Graphics Lcd Controller
• Manufacturer: Epson Electronics America, Inc.

Page 34
4 DISPLAY MEMORY MODELS
4.1 Registers
bit 1
AUX[06] bits 7-0 Screen 1 Display Start Address Bits [15:0]
AUX[07] bits 7-0 These 16 bits determine the Screen 1 Display Start Address. In an 8-bit memory configuration these bits
S1D13503
X18A-G-002-06
AUX[06] Screen 1 Display Start Address Register (LSB)
I/O address = 0110b, Read/Write.
Screen 1
Display Start
Addr
Bit 7
AUX[01] Mode Register 0
I/O address = 0001b, Read/Write.
DISP
AUX[07] Screen 1 Display Start Address Register (MSB)
I/O address = 0111b, Read/Write.
Screen 1
Display
Start Addr
Bit 15
This section includes a concise description of the Display Start Address Registers, followed by a description of display
memory. Afterwards examples are provided, illustrating how to calculate the display memory model for a given display
resolution and color/gray level mode. Once this model is calculated, examples on programming the Display Start Address
Registers are provided.
Register bits discussed in this section are highlighted.
Note
The absolute address into display memory is determined by the Memory Mapping
Address which is set by the reset state of VD13 - VD15.
Screen 1
Display Start
Addr
Bit 6
Screen 1
Display
Start Addr
Bit 14
Panel
Memory Interface
This bit selects between the 8-bit or 16-bit memory interface. When this bit = 0, the 16-bit memory inter-
face is selected. When this bit = 1, the 8-bit memory interface is selected. If 16-bit bus interface (VD0 = 1
on RESET) or 256 color mode (AUX[03] bits 2-1 = 11) is selected, the Memory Interface bit is forced to 0
internally (16-bit). This bit goes low on RESET.
set the 16-bit start address (i.e., byte access). In a 16-bit memory configuration these are the 16 most sig-
nificant bits of a 17-bit start address (i.e., word access).
The Screen 1 Display Start Address is the memory address corresponding to the first displayed pixel (top
left corner). In a dual panel configuration, screen 1 refers to the upper half of the display. While in a single
panel configuration, screen 1 refers to the first screen of the Split Screen Display feature where two differ-
ent images (screen 1 and screen 2) can be displayed at the same time on one display.
Screen 1
Display Start
Addr
Bit 5
Screen 1
Display
Start Addr
Bit 13
Mask
XSCL
Screen 1
Display Start
Addr
Bit 4
Screen 1
Display
Start Addr
Bit 12
LCDE
Screen 1
Display Start
Addr
Bit 3
Screen 1
Display
Start Addr
Bit 11
Gray Shade /
Color
Screen 1
Display Start
Addr
Bit 2
Screen 1
Display
Start Addr
Bit 10
LCD Data
Width Bit 0
Epson Research and Development
Screen 1
Display Start
Addr
Bit 1
Screen 1
Display
Start Addr
Bit 9
Programming Notes and Examples
Memory
Interface
Vancouver Design Center
Screen 1
Display Start
Addr
Bit 0
Screen 1
Display
Start Addr
Bit 8
Issue Date: 01/01/30
RAMS