LM5060Q1 National Semiconductor Corporation, LM5060Q1 Datasheet - Page 17

• Manufacturer Part Number: LM5060Q1
• Description: High-side Protection Controller With Low Quiescent Current
• Manufacturer: National Semiconductor Corporation

Where I
V
(0.068 μF) the V
be:
Should a subsequent load current surge trip the V
Comparator, the timer capacitor discharge transistor turns
OFF and the 11 μA (typical) current source begins linearly
charging the timer capacitor. If the surge current, with the de-
tected excessive V
capacitor to charge to the timing comparator threshold
(V
charge the MOSFET gate and latch the MOSFET off. The
V
lated from:
Where I
C
delay time would typically be:
Since a single capacitor is used to set the delay time for mul-
tiple fault conditions, it is likely that some compromise will
need to be made between a desired delay time and a practical
delay time.
MOSFET SELECTION
The external MOSFET (Q1) selection should be based on the
following criteria:
•
•
•
•
•
•
INPUT and OUTPUT CAPACITORS
Input and output capacitors are not necessary in all applica-
tions. Any current that the external MOSFET conducts in the
on-state will decrease very quickly as the MOSFET turns off.
V
TMRL
DS
TIMER
DS
TMRH
The BV
system voltage (V
occur at V
The maximum transient current rating should be based on
the maximum worst case V
MOSFETs with low threshold voltages offer the advantage
that during turn on they are more likely to remain within
their safe operating area (SOA) because the MOSFET
reaches the ohmic region sooner for a given gate
capacitance.
The safe operating area (SOA) of the MOSFET device and
the thermal properties should be considered relative to the
maximum power dissipation possible during startup or
shutdown.
R
dissipation at maximum load current ((I
does not increase the junction temperature above the
manufacturer’s recommendation.
If the device chosen for Q1 has a maximum V
than 16V, an external zener diode must be added from
gate to source to limit the applied gate voltage. The
external zener diode forward current rating should be at
least 80 mA to conduct the full gate pull-down current
during fault conditions.
V
fault delay time during an Over-Current event is calcu-
DS(ON)
Fault Delay = (((2V-0.3V) x 0.068 μF) / 11 μA) = 10 ms
DS
) of typically 2V, the LM5060 will immediately dis-
is typically 300 mV. If the C
value is 68 nF (0.068 μF) the V
TMRH
TMRH
Fault Delay = ((2V x 0.068 μF) / 11 μA) = 12 ms
DSS
should be sufficiently low that the power
is typically 11 μA and V
IN
is typically 11 μA, V
rating must be greater than the maximum
when the circuit is powered on or off.
DS
DS
transition fault delay time would typically
IN
voltage, lasts long enough for the timer
), plus ringing and transients which can
DS
fault current level.
TMRH
TMRH
TIMER
DS
is typically 2V, and
is typically 2V. If the
Over-Current fault
L(MAX)
value is 68 nF
GS
)
2
x R
rating less
DS
DS(ON)
Fault
)
17
All trace inductances in the design including wires and printed
circuit board traces will cause inductive voltage kicks during
the fast termination of a conducting current. On the input side
of the LM5060 circuit this inductive kick can cause large pos-
itive voltage spikes, while on the output side, negative voltage
spikes are generated. To limit such voltage spikes, local ca-
pacitance or clamp circuits can be used. The necessary ca-
pacitor value depends on the steady state input voltage level,
the level of current running through the MOSFET, the induc-
tance of circuit board traces as well as the transition speed of
the MOSFET.
Since the exact amount of trace inductance is hard to predict,
careful evaluation of the circuit board is the best method to
optimize the input or output capacitance or clamp circuits.
UVLO, OVP
The UVLO and OVP thresholds are programmed to enable
the external MOSFET (Q1) when the input supply voltage is
within the desired operating range. If the supply voltage is low
enough that the voltage at the UVLO pin is below the UVLO
threshold, Q1 is switched off by a 2.2 mA (typical) current sink
at the GATE pin, denying power to the load. The UVLO
threshold has approximately 180 mV of hysteresis.
If the supply voltage is high enough that the voltage at the
OVP pin is above the OVP threshold, the GATE pin is pulled
low with a 80 mA current sink. Hysteresis is provided for each
threshold. The OVP threshold has approximately 240 mV of
hysteresis.
Option A: The configuration shown in
resistors (R1, R2, and R3) to set the thresholds.
FIGURE 9. UVLO and OVP Thresholds Set By R1, R2 and
The procedure to calculate the resistor values is as follows:
1. Select R1 based on current consumption allowed in the
resistor divider and consideration of noise sensitivity. Values
between 10 kΩ and 200 kΩ are suggested.
2. Calculate R3 with the following formula:
R3
Figure 9
requires three
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