AMIS-30521 AMI Semiconductor, Inc., AMIS-30521 Datasheet - Page 14

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AMIS-30521

Manufacturer Part Number
AMIS-30521
Description
Micro-stepping Motor Driver
Manufacturer
AMI Semiconductor, Inc.
Datasheet
AMIS-30521 Micro-stepping Motor Driver
The following drawing illustrates the operation of the SLA-pin and the transparency-bit. "PWMsh" and "Icoil=0" are internal signals that
define together with SLAT the sampling and hold moments of the coil voltage.
8.6 Warning, Error Detection and Diagnostics Feedback
8.6.1. Thermal Warning and Shutdown
When junction temperature rises above T
temperature increases above thermal shutdown level, then the circuit goes in “thermal shutdown” mode (<TSD>) and all driver
transistors are disabled (high impedance)
temperature lower than T
8.6.2. Over-Current Detection
The over-current detection circuit monitors the load current in each activated output stage. If the load current exceeds the over-current
detection threshold, then the over-current flag is set and the drivers are switched off to reduce the power dissipation and to protect the
integrated circuit. Each driver transistor has an individual detection bit in the
Register 2
the drivers.
AMI Semiconductor – June 2007, M-20683-001
www.amis.com
(<OVCXij> and <OVCYij>). Error condition is latched and the microcontroller needs to clean the status bits to reactivate
SLA-pin
PWMsh
Icoil=0
SLAT
V
COIL
PWMsh
V
Icoil=0
COIL
SLAT=1 => SLA-pin is "transparent" during
Crossing. SLA-pin is updated "real-time".
V
TW
BEMF
div2
div4
and to clear the <TSD> flag by reading it using any SPI read command.
sampling @ Coil Current Zero
Ssh
TW
(Table 29: SPI Status Register
Csh
, the thermal warning bit <TW> is set
Figure 13: Timing Diagram of SLA-pin
Sh
last sample
is retained
Ch
SLA-pin is updated when leaving current-less state.
V
BEMF
14
SLAT=0 => SLA-pin is not "transparent" during
V
BEMF
SLAT
NOT(Icoil=0)
previous output is kept at SLA pin
buf
sampling @ Coil Current Zero Crossing.
Table 28: SPI Status Register 1
SLA-pin
2). The conditions to reset flag <TSD> is to be at a
(Table 27: SPI Status Register
retain last sample
t
and
t
PC20070604.8
Table 29: SPI Status
Data Sheet
0). If junction

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