AMIS-30521 AMI Semiconductor, Inc., AMIS-30521 Datasheet - Page 15

• Manufacturer Part Number: AMIS-30521
• Description: Micro-stepping Motor Driver
• Manufacturer: AMI Semiconductor, Inc.

AMIS-30521 Micro-stepping Motor Driver
8.6.3. Open Coil Detection
Open coil detection is based on the observation of 100 percent duty cycle of the PWM regulator. If in a coil 100 percent duty cycle is
detected for longer than 200ms then the related driver transistors are disabled (high-impedance) and an appropriate bit in the SPI
status register is set (<OPENX> or <OPENY>).
8.6.4. Charge Pump Failure
The charge pump is an important circuit that guarantees low Rdson for all drivers, especially for low supply voltages. If supply voltage
is too low or external components are not properly connected to guarantee Rdson of the drivers, then the bit <CPFAIL> is set in the
Table 27: SPI Status Register
threshold. During that time <CPFAIL> will be set to “1”.
8.6.5. Error Output
This is a digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic combination
of:
8.7 CLR pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip. To reset the complete digital inside AMIS-30521, the input CLR needs to be
pulled to logic 1 during minimum time given by T
the need of a power-cycle. The operation of all analog circuits is depending on the reset state of the digital, charge pump remains
active. Logic 0 on CLR pin resumes normal operation again.
8.8 Sleep Mode
The bit <SLP> in
consumption when the motor is not in operation. The effect of sleep mode is as follows:
Normal operation is resumed after writing logic ‘0’ to bit <SLP>. A start-up time is needed for the charge pump to stabilize. After this
time, NXT commands can be issued.
AMI Semiconductor – June 2007, M-20683-001
www.amis.com
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The drivers are put in HiZ
All analog circuits are disabled and in low-power mode
All internal registers are maintaining their logic content
NXT and DIR inputs are forbidden
SPI communication remains possible (slight current increase during SPI communication)
Reset of chip is possible through CLR pin
Oscillator and digital clocks are silent, except during SPI communication
Table 15: SPI Control Register 2
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR < OVCYij> OR <OPENi> OR <CPFAIL>
0. Also after power-on-reset the charge pump voltage will need some time to exceed the required
(Table 27: SPI Status Register
CLR
is provided to enter a so-called “sleep mode”. This mode allows reduction of current-
.
(Table 6: AC
15
Parameters) This reset function clears all internal registers without
0)
Data Sheet