PIC16C765 Microchip Technology Inc., PIC16C765 Datasheet - Page 87

• Manufacturer Part Number: PIC16C765
• Description: 8-bit Cmos Microcontrollers With Usb
• Manufacturer: Microchip Technology Inc.

11.3.2
Once Synchronous mode is selected, reception is
enabled
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set, CREN takes precedence. After clocking the last bit,
the received data in the Receive Shift Register (RSR)
is transferred to the RCREG register (if it is empty).
When the transfer is complete, interrupt flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be enabled/
disabled
(PIE1<5>). Flag bit RCIF is a read only bit, which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register, i.e., it is a two
deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
TABLE 11-9:
Address
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous master reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C745; always maintain these bits clear.
2000 Microchip Technology Inc.
USART SYNCHRONOUS MASTER
RECEPTION
by
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
by
Name
setting
setting/clearing
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
USART Receive Register
Baud Rate Generator Register
PSPIF
PSPIE
SPEN
CSRC
Bit 7
either
(1)
(1)
ADIF
ADIE
Bit 6
RX9
TX9
enable
enable
SREN
TXEN
RCIF
RCIE
Bit 5
bit
bit
CREN
SYNC
Bit 4
TXIF
TXIE
SREN
RCIE
Preliminary
USBIF
USBIE CCP1IE
Bit 3
—
—
CCP1IF
it is essential to clear bit OERR if it is set. The ninth
receive bit is buffered the same way as the receive
data. Reading the RCREG register will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
Steps to follow when setting up a Synchronous Master
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
BRGH
FERR
Bit 2
Initialize the SPBRG register for the appropriate
baud rate (Section 11.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit RCIE.
If 9-bit reception is desired, then set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
TMR2IF
TMR2IE
OERR
TRMT
Bit 1
PIC16C745/765
TMR1IF
TMR1IE
RX9D
TX9D
Bit 0
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on:
POR,
BOR
DS41124C-page 87
other Resets
Value on all
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000